Routing Flow

Route Clock nets

↓

Route signal nets

↓

optimize trace topology

↓

Post route clock tree optimization

↓

all nets routed

↓

skew and timing ok? no→ Post route CTO
↓yes
Search and repair

Route clock nets:
To meet the specified insertion delay and skew it is necessary that clock nets be routed first, they can have the most direct-routing.
This also indicates to route the critical signals and buses in the design.


Route signal nets:
After the critical nets are routed the signal nets non-critical ca be routed.The process of routing is timing-driven.Routing of timing critical path is given highest priority in order to maintain the overall timing so that the route is as short as possible.Nets that are non-critical are routed around critical areas to provide more wiring area for critical nets.



Post route CTO:
Minor clock skew and timing violations may have been introduced by previous routing and optimization steps,which are fixed in this step.

Routing

The objective of routing:

• Create metal connections to all clock and signal pins.
• Metal traces must meet physical DRC requirements.
• Minimize total wire length, the total number of vias ,completing the connections without increasing the chip area.
• Each net meet its timing budget.

After placement step, the exact locations of the cells and pins are fixed.Now physical connections defined in the netlist needs to be done in the routing step.This is done using wires(metal) to connect the terminals in each net.

The process of finding geometric layout for the nets is called routing.

The objective of routing depend on the nature of design.
In general purpose design, it is sufficient to minimize the total length of the wire while completing the physical connections.
In high performance designs it is crucial to meet the timing target,and also there are special purpose nets like clock, power and ground nets which require special treatment.
Metal traces must meet design rule reuirements.


A chip might contain millions of transistor and as a result millions of net needs to be routed to complete the layout.To find the best possible way to route is difficult to compute.

Steps in routing:

Global routing:
In global routing, a loose route for each net is generated.It assigns a list of routing regions to each net without specifying the actual geometric layout of the wires.
Global routing cells are defined , their size is equal to height of the average standard cells.
Global route determine whether each assigned GRC along a path has enough wire tracks for assigned nets through the edges of that GRC.If there are not enough wire tracks ,global route reassigns metal layers and global route cells accordingly.




















Global route gives more accurate parasitic and delay estimates compared to virtual route.


Track assignment:
Assign each net to a specific track and lays down actual metal traces.
It also attempts to:

• make long straight traces.
• reduce the no of vias.

Track assignment does not follow DRC rules.



Detail routing:
It performs actual physical interconnections of the design.Detail router can grid based or grid less.

Grid based routing:
Grid based routing imposes routing grid (evenly spaced routing tracks running both vertically and horizontally across the design area) that all routing segments must follow.The router is allowed o change direction at the intersection of vertical and horizontal tracks.

The advantage of grid based routing is efficiency. When using a grid based router , one needs to make sure that the ports of all instances are on grid otherwise they can create physical design rule errors which would be difficult to resolve.


Metal traces or routes are created and centered on routing tracks. Each metal layer has its own track and preferred routing direction.These metal routes must meet minimum width and spacing requirements to prevent defects during fabrication.

M1-horizontal
M2-vertical

The tracks and preferred routing direction are defined in the unit tile cell in the standard cell library.The design rule spacing and widths in the technology file for each metal layer which are not checked during the track assignment phase.These rules are checked in detail routing and search and repair phase.Detail routing tries to fix the design rules (minimum width, spacing, etc) which were violated during track assignment.





Grid-based systems use these pitches (width + spacing) to determine the minimum center to center space for each metal layer. The design rule information to form this grid is located in the technology file for each metal layer.
































Routing Design rule:
Minimum length rule:
To specify the minimum wire length allowed.

Notch spacing:
While routing if the net creates spacing violations to itself(same metal) it is notch violation.
Notch rule specifies minimum notch width and height.


Defining Minimum Via Spacing Rules in the Same Net or different net.







Metal Density rule:
The total percentage of the named metal layer in the window size will be within the specified minimum and maximum density limits.



Search and Repair:
The design is broken into switch boxes of fixed sizes, DRC violations are fixed through multiple loops and each time S-box is made progressively larger to incorporate the larger portion of the design.

The search and repair stage is the last step in the routing process. Once search and repair has resolved all design rule violations, the design is considered to have been placed and routed and ready for verification and fabrication.






























Congestion:
A major problem with grid based routing is congestion of metal routes.Congestion results when there are more wires in the design to route than the tracks available.Typically only small areas of the design experience congestion in which standard cells can be moved accordingly. If the congestion is severe, more extreme measures may need to be taken such as the moving of macros or the re-floor planning of the entire design.

standard cell delay

The propagation delay in a standard cell is given by average of two time intervals.


tp = (th+ tr)/2

Propagation delay is the time difference between approximately 50% of the input transition and 50% of the output transition.

If the input waveform changes from zero to supply voltage (VDD) or from supply
voltage (VDD) to zero value, then low-to-high and high-to-low propagation
delays can be expressed as
tplh = ClVdd/(beta)p(Vdd-|vtp|)2
tphl = clVdd/(beta)p(Vdd - |vtn|)2

to improve the propagation delay of a given standard cell, one could
Increase supply voltage,
Reduce threshold voltage,
Increase transistors gain factors, or
Reduce the load capacitance.

Reducing load capacitance and increasing supply voltage is outside the standard cell.
Reduction of threshold voltage depends on semiconductor foundry and is part of the standard cell characterization.The only available parameter to the circuit designer is to increase gain factor.

the length and width of the transistor are related to gain factor beta.

In Wp/Wn ratio determination, it is desired to set

betan = k betap.
Wp/Wn = 2/k

In the ideal situation, k is equal to 1. This means that for a CMOS inverter to
charge and discharge capacitive loads in the same amount of time, the
channel width of the PMOS transistor must be twice as large as the channel
width of the NMOS transistor.

Although increasing the value of Wp / Wn reduces the cell propagation
delay, it also increases the active area capacitance and gate capacitance. This
increase in capacitance adversely affects the gate speed. Therefore, circuit
designers must make a trade off in determining how large the transistors
should be such that their propagation delays are optimal.

Fast circuits consume more area than slow circuits.

Steps in Placement

Detach Scan chain and Scan chain reordering:

what is a scan chain?
Scan chain is one of the DFT strategies to improve chip's observability and controllability.It is collection of flip flops connected by scan chain.In the chain the output of the previous flip flop is
connected to the scan data input of the next flip flop.The data is sent to scan input and output of the logic operation is observed at the scan output.The nodes along the scan chain can be set to intended value 0 or 1 by the scan chain.The effect of these settings can be seen by shifting the data through out the scan chain, controlled and observed.

Physical wire connection between adjacent flip flops depends on the logical order of the chain.Logical proximity does not match with physical proximity.

Logical order is decided during logic synthesis stage through the random process or alphabetical order since physical locations are unknown at that time.
As a result if the original chains are retained, then routing,physical wire connections will not be optimized.

Best approach is to disconnect the scan chain before placement , so that the normal placement will not be disturbed by the connectivity of the scan chains.Then reorder the chain arrangement after the placement step after all the physical locations are fixed and known.The reordering based on physical location information improves overall routability and total connecting wire length.


All WLM (wire load models ) are removed before performing timing optimization and timing is calculated based on VR virtual route.Virtual route is the shortest Manhattan distance between two pins.

Manhattan right angle ruler for backend.It is also called as city-block distance. It is so named because it is the distance a car would drive in a city laid out in square blocks, like Manhattan (discounting the facts that in Manhattan there are one-way and oblique streets and that real streets only exist at the edges of blocks - there is no 3.14th Avenue). Any route from a corner to another one that is 3 blocks East and 6 blocks North, will cover at least 9 blocks.

The distance between the two points measured along axes at right angles.

Set Placement and timing options:
No cells under the preroute of the metal layer and under the via selected.
P & R tool prevents pins of standard cells from being placed under the metal layers you specify. This means that a standard is not be placed in a location when any pin of the cell overlaps with a preroute of the metal layer. For example, if M3 is selected, a standard cell will not be placed when any of its pins (regardless of the pin’s metal layer) overlaps with a preroute on M3.

Avoiding pin overlap with preroutes improves routability because there are less routing resources under preroutes due to the preroute and any vias and contacts along the preroutes.

Placement optimization:
PrePlace optimization:

1. It generates the initial placement before optimizing the netlist to get the wiring information.
2. It collapses non-critical buffer, reduces total cell area by downsizing so that the netlist is easier to place.
3. High fanout nets contain significantly large number of buffers which can impact placement so,instead of minimizing the buffer , it rebuilds the HFN nets based on more accurate RC estimates.
4. Performs quick logic synthesis.
   

In -Placement optimization:

1. Places all the standard cells.
2. It re-optimizes the logic based on virtual route.It does cell sizing,area recovery, gate duplication,buffer insertion,net splitting.Optimizes the gates for setup timing based on virtual route.
3. incremental timing, and congestion-driven placement.

Post Placement optimization before CTS:

1. Optimization is done with ideal clocks.
2. It performs a more specific timing optimization of the netlist and the layout, including quick fixing of setup and hold violations and maximum transition and maximum capacitance violations by buffering the gates.
3. It can do placement optimization based on global routing.

Post Placement optimization after CTS:

Effect of CTS:

• Clock buffers are added.
• Congestion may increase.
• Non clock tree cells may have been moved to less ideal locations.
• Can introduce new timing and max tran/cap violation.

• Post-placement optimization after clock tree synthesis improves the timing results of your design with propagated clocks. It takes the clock tree into account so that the clock skew can be preserved. Post-placement optimization after clock tree synthesis has an option to perform congestion removal before running optimization
• Perform logical and placement optimization to fix timing and max cap/tran violation.
• Fixing hold time is recommended here.
• Reduce congestion by removing unnecessary non-clock tree buffers.

Critical range optimization:

Worst negative slack corresponds to the path having maximum negative slack.
Total negative slack is the summation of all WNS per end point.

When TNS >> WNS, there might be sub critical path violations which are as good as the critical path violations.
Optimization during placement mainly works on the critical path of each clock domain and stops when it cannot further improve timing.
Critical range optimization works on sub -critical paths to reduce TNS and the total number of violation paths.

Iterate Post placement optimization and critical range optimization until remaining violations are acceptably small and if further improvement are seen.


Timing Driven Placement
P & R tool requires timing constraints to understand design timing objectives.The most standard
timing constraints on most designs include arrival times of the input signals to the design as well as the required arrival time at the output of the chip.This also include clock period of the system clock and as well as other clocks if the design contains multiple clock domains.

The timing information that tool uses is based upon the standard cell delays and wire connected to all these cells in the design.
The standard cell delays are the function of input transition and as well as the summation of capacitance of output wire and input gates of all the logic connected to the output wire.
Wire delays are the function of resistance of the metal layers and summation of wire capacitance and input gate capacitance.


Timing driven placement is the process of placing the standard cells in the rows of the core area using timing constraints as the guidelines as to where to place the cells.


Evaluation of Placement:
After performing automatic placement, evaluate the placement and make changes to improve the routability of the design.
During placement, tool calculates routing congestion, based on the availability of wire tracks inside the global routing cells. Using these routing congestion calculations, It produces a placement congestion map that shows the estimated amount of routing congestion within the design.

Placement objectives

what is Placement?
Placement is process of placing the cells,searching for appropriate place within the floorplan of the chip for each cell in the netlist.

Placement objectives:
-Guarantee the router can complete routing step
-minimize critical net delay
-make the chip as dense as possible.

Placement additional objectives are as follows:
Minimize the estimated interconnect length.
Meet the timing requirements for the critical nets
Minimize interconnect congestion

Channel definition and Slicing Floor Plan

During the floor plan we assign the areas between the blocks for interconnect.This is called channel definition or channel allocation

T-shaped junction between two rectangular channels










Routing a T-junction between two channels in two-level metal. The dots represent logic cell pins. (a) Routing channel A (the stem of the T) first allows us to adjust the width of channel B. (b) If we route channel B first (the top of the T), this fixes the width of channel A. We have to route the stem of a T-junction before we route the top.

Channel ordering:
Choosing the order of rectangular channel to route is channel ordering.

Slicing Floor Plan:
Suppose a chip has several blocks.We cut along the block boundaries in the chip into two pieces.
And we continue in the same manner until we separate all the blocks is called slicing floorplan.













Defining the channel routing order for a slicing floorplan using a slicing tree. (a) Make a cut all the way across the chip between circuit blocks. Continue slicing until each piece contains just one circuit block. Each cut divides a piece into two without cutting through a circuit block. (b) A sequence of cuts: 1, 2, 3, and 4 that successively slices the chip until only circuit blocks are left. (c) The slicing tree corresponding to the sequence of cuts gives the order in which to route the channels: 4, 3, 2, and finally 1.

It shows how the sequence we use to slice the chip defines a hierarchy of the blocks. Reversing the slicing order ensures that we route the stems of all the channel T-junctions first.

Cyclic constraint and non-slicing floorplan:











Non -slicing floor plan is the one where we cannot cut the chip into pieces without chopping a circuit block into two.We cannot route a channel until other channels are routed.This is called cyclic constraint.
The only solution to remove the cyclic constraint is to move the block, but this will make it area inefficient,routing difficult.We may have to use area based router or L-shaped or switch boxes(fixed connectors) for routing.












Channel definition and ordering. (a) We can eliminate the cyclic constraint by merging the blocks A and C. (b) A slicing structure.

We can also merge circuit blocks since it is more efficient to route the row -based block by flattening them than route between the blocks.Now , we get a slicing floorplan .Fig(b) shows the channel definition and routing order for our chip.