When Vin is high and equal to Vdd,the NMOS transistor is on,while PMOS transistor is off.A direct path exist between Vout and ground node,resulting steady-state value of 0v.On the other hand , when Vin is low (0v),NMOS and PMOS transistors are off and on respectively.A direct path exist between Vdd and Vout yielding a high output voltage.
Other important properties:
- The high and low output levels equal VDD and GND, respectively; in other words,the voltage swing is equal to the supply voltage. This results in high noise margins.
- The logic levels are not dependent upon the relative device sizes, so that the transistors can be minimum size. Gates with this property are called ratioless.
- In steady state , there always exists a path with finite resistance between the output and either Vdd or Gnd.A well-designed CMOS inverter ,therefore has a low output impedances, which makes it less sensitive to noise and disturbances.
- The input resistance of the CMOS inverter is extremely high , as the gate of MOS transistor is a virtually perfect insulator and draws no dc input current.Since the input node of the inverter only connect to transistor gates,the steady state input current is nearly zero.
- A single inverter can theoretically have infinite fanout and still be functionally operational.However, increasing fan-out also increases propagation delay.
- No direct path exist between VDD and gnd under steady state operating condition,absence of current indicates that the gate does not consume any static power.
