what is Placement?
Placement is process of placing the cells,searching for appropriate place within the floorplan of the chip for each cell in the netlist.
Placement objectives:
-Guarantee the router can complete routing step
-minimize critical net delay
-make the chip as dense as possible.
Placement additional objectives are as follows:
Minimize the estimated interconnect length.
Meet the timing requirements for the critical nets
Minimize interconnect congestion
Thursday, April 22, 2010
Channel definition and Slicing Floor Plan
During the floor plan we assign the areas between the blocks for interconnect.This is called channel definition or channel allocation
T-shaped junction between two rectangular channels
Routing a T-junction between two channels in two-level metal. The dots represent logic cell pins. (a) Routing channel A (the stem of the T) first allows us to adjust the width of channel B. (b) If we route channel B first (the top of the T), this fixes the width of channel A. We have to route the stem of a T-junction before we route the top.
Channel ordering:
Choosing the order of rectangular channel to route is channel ordering.
Slicing Floor Plan:
Suppose a chip has several blocks.We cut along the block boundaries in the chip into two pieces.
And we continue in the same manner until we separate all the blocks is called slicing floorplan.
Defining the channel routing order for a slicing floorplan using a slicing tree. (a) Make a cut all the way across the chip between circuit blocks. Continue slicing until each piece contains just one circuit block. Each cut divides a piece into two without cutting through a circuit block. (b) A sequence of cuts: 1, 2, 3, and 4 that successively slices the chip until only circuit blocks are left. (c) The slicing tree corresponding to the sequence of cuts gives the order in which to route the channels: 4, 3, 2, and finally 1.
It shows how the sequence we use to slice the chip defines a hierarchy of the blocks. Reversing the slicing order ensures that we route the stems of all the channel T-junctions first.
Cyclic constraint and non-slicing floorplan:
Non -slicing floor plan is the one where we cannot cut the chip into pieces without chopping a circuit block into two.We cannot route a channel until other channels are routed.This is called cyclic constraint.
The only solution to remove the cyclic constraint is to move the block, but this will make it area inefficient,routing difficult.We may have to use area based router or L-shaped or switch boxes(fixed connectors) for routing.
Channel definition and ordering. (a) We can eliminate the cyclic constraint by merging the blocks A and C. (b) A slicing structure.
We can also merge circuit blocks since it is more efficient to route the row -based block by flattening them than route between the blocks.Now , we get a slicing floorplan .Fig(b) shows the channel definition and routing order for our chip.
T-shaped junction between two rectangular channels
Routing a T-junction between two channels in two-level metal. The dots represent logic cell pins. (a) Routing channel A (the stem of the T) first allows us to adjust the width of channel B. (b) If we route channel B first (the top of the T), this fixes the width of channel A. We have to route the stem of a T-junction before we route the top.
Channel ordering:
Choosing the order of rectangular channel to route is channel ordering.
Slicing Floor Plan:
Suppose a chip has several blocks.We cut along the block boundaries in the chip into two pieces.
And we continue in the same manner until we separate all the blocks is called slicing floorplan.
Defining the channel routing order for a slicing floorplan using a slicing tree. (a) Make a cut all the way across the chip between circuit blocks. Continue slicing until each piece contains just one circuit block. Each cut divides a piece into two without cutting through a circuit block. (b) A sequence of cuts: 1, 2, 3, and 4 that successively slices the chip until only circuit blocks are left. (c) The slicing tree corresponding to the sequence of cuts gives the order in which to route the channels: 4, 3, 2, and finally 1.
It shows how the sequence we use to slice the chip defines a hierarchy of the blocks. Reversing the slicing order ensures that we route the stems of all the channel T-junctions first.
Cyclic constraint and non-slicing floorplan:
Non -slicing floor plan is the one where we cannot cut the chip into pieces without chopping a circuit block into two.We cannot route a channel until other channels are routed.This is called cyclic constraint.
The only solution to remove the cyclic constraint is to move the block, but this will make it area inefficient,routing difficult.We may have to use area based router or L-shaped or switch boxes(fixed connectors) for routing.
Channel definition and ordering. (a) We can eliminate the cyclic constraint by merging the blocks A and C. (b) A slicing structure.
We can also merge circuit blocks since it is more efficient to route the row -based block by flattening them than route between the blocks.Now , we get a slicing floorplan .Fig(b) shows the channel definition and routing order for our chip.
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