So that i would get a chance to visit fab once in my lifetime,hoping for the best.
Monday, April 5, 2010
what is physical design?
The process of converting the design of a system into layout ,which can then be fabricated is known as physical design.
what do you require for doing physical design?
In other words what are the inputs to the physical design.
I had used tool synopsys Place and route tool ASTRO , what inputs does ASTRO need?
1.Gate level netlist.
2.Library.
3.Technology file.
4.TLU+.
5.Synopsys design constraints (SDC).
Let us see why do we require ?Where do we get it from?What is the use of it?
1.Gate level netlist:
why? of course we get the design from gate level netlist, it is description of the architecture and function of the design.It is mapped to standard cell library ,logic optimization was carried on the design in order to meet the constraints before generating this netlist during synthesis stage.
Where do we get it from?
In front end we generate the gate level netlist at the synthesis stage, where it combines the RTL code and design constraints and produces final gate level netlist which can be interpreted by P & R tool.
what is the use of it?
P & R tool consider this as "golden netlist" for all stages in physical design.Finally netlist generated after the Place and route is compared with the original netlist to verify that functionality is changed.
2.Standard cell library :
Why ?
a)Our design will be made up of logic functions like AND,OR etc,so standard cell library consists of list of logic functions -AND,OR etc.
b)We will be concerned about physical shapes of the logic functions.
Standard cell library provides
1.Abstract view describing I/O and location of metal pins.
2. Layout view describing the mask layers required in fabrication.
c) It also provides timing information such as
1.Cell delay
2.Input capacitance etc
This will help ASTRO to perform static timing analysis during physical design process.
d) Very importantly , standard cell (different logic function)in the library have fixed height but variable width depending upon their driving strength.
There are other libraries which may be required:
custom cells -I/O ,reusable Intellectual property (IP) cores ,RAM.
Where do we get it from?
It is usually supplied by the vendor or generated manually.
3.Technology file:
why?
Ultimately our design need to fabricated which will be 180nm,or 130nm,90nm process.
All the process specific data is given in tech file.
a) It has process design rules to help ASTRO do De.sign rule check.
b)Process specific information-mask layer info,metal layer info -their resistance and capacitance values so that ASTRO can estimate the delay introduced while routing.
via definitions used for connection of metal ,metal attributes-metal spacing ,width,color .
where do we get it from?
Fab .
4.TLU+
why?
Look up table -which contains resistance and capacitance values of metal layers for the ASTTRO to estimate the delay on particular route.
5.SDC.
Where do we get it from?
SDC is derived from design specification.
Why?
Design of system will have certain specifications to be met.After fabrication it should meet the specifications.Speed , area and power are the three features which we look into.
SDC provided in the front end is also given as input to the physical design in order to meet the constraints.
I had used tool synopsys Place and route tool ASTRO , what inputs does ASTRO need?
1.Gate level netlist.
2.Library.
3.Technology file.
4.TLU+.
5.Synopsys design constraints (SDC).
Let us see why do we require ?Where do we get it from?What is the use of it?
1.Gate level netlist:
why? of course we get the design from gate level netlist, it is description of the architecture and function of the design.It is mapped to standard cell library ,logic optimization was carried on the design in order to meet the constraints before generating this netlist during synthesis stage.
Where do we get it from?
In front end we generate the gate level netlist at the synthesis stage, where it combines the RTL code and design constraints and produces final gate level netlist which can be interpreted by P & R tool.
what is the use of it?
P & R tool consider this as "golden netlist" for all stages in physical design.Finally netlist generated after the Place and route is compared with the original netlist to verify that functionality is changed.
2.Standard cell library :
Why ?
a)Our design will be made up of logic functions like AND,OR etc,so standard cell library consists of list of logic functions -AND,OR etc.
b)We will be concerned about physical shapes of the logic functions.
Standard cell library provides
1.Abstract view describing I/O and location of metal pins.
2. Layout view describing the mask layers required in fabrication.
c) It also provides timing information such as
1.Cell delay
2.Input capacitance etc
This will help ASTRO to perform static timing analysis during physical design process.
d) Very importantly , standard cell (different logic function)in the library have fixed height but variable width depending upon their driving strength.
There are other libraries which may be required:
custom cells -I/O ,reusable Intellectual property (IP) cores ,RAM.
Where do we get it from?
It is usually supplied by the vendor or generated manually.
3.Technology file:
why?
Ultimately our design need to fabricated which will be 180nm,or 130nm,90nm process.
All the process specific data is given in tech file.
a) It has process design rules to help ASTRO do De.sign rule check.
b)Process specific information-mask layer info,metal layer info -their resistance and capacitance values so that ASTRO can estimate the delay introduced while routing.
via definitions used for connection of metal ,metal attributes-metal spacing ,width,color .
where do we get it from?
Fab .
4.TLU+
why?
Look up table -which contains resistance and capacitance values of metal layers for the ASTTRO to estimate the delay on particular route.
5.SDC.
Where do we get it from?
SDC is derived from design specification.
Why?
Design of system will have certain specifications to be met.After fabrication it should meet the specifications.Speed , area and power are the three features which we look into.
SDC provided in the front end is also given as input to the physical design in order to meet the constraints.
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