I/O Pad Placement

There are three types of I/O pads:

1. Power
2. Ground
3. Signal

It is necessary to ensure that the i/o pads have adequate power and ground connections ,placed properly to avoid electromigration and current switching noise.

Electromigration:
It is the movement of molecular atoms from one are to another area caused by excessive flowof current in the direction of flow of electrons.It results in shorts between electric wires, hillocks, high metal resistance causing ASIC failure.

No of pads can be determined by Ngnd = Itotal/Imax

Ngnd -No of ground pads
Itotal -ASIC total current
Imax -Maximum EM current in amperes /ground pad.



















Switching noise:
switching noise is generated when ASIC output make transitions from one state to another.
Insufficient ground and power pads may lead to data errors due to switching noise transitions.

1.Capacitive coupling
dv/dt
It is the disturbance caused in adjacent package pin when switching transients inject pulses via parasitic capacitive coupling.

This can be reduced by:
1.Isolate sensitive clock inputs pin from the switching signal pads.
2.Group bidirectional pads together so that all are in either input or output mode.

2.Inductive coupling
Simultaneous switching of the ASIC output induces rapid current changes in power and ground busses.The inductance in power and ground pins causes voltage fluctuations in internal ASIC power and ground level.

The rapid current changes may induce logic error or may cause noise spikes on non-switching output pads that affect signals connected to other systems.

The maximum L (di/dt) occurs when ASIC output make a transition to another voltage level and
absolute current increases from zero through a wire of inductance L.Factors such as process, ambient temperature, voltage, location of output pads, and number of simultaneous
switching output pads determine the magnitude of inductive switching noise.


To control inductive switching noise, enough power and ground pads mustbe assigned and placed correctly. This way the noise magnitude will be limited. This noise reduction will prevent inputs of ASIC design from interpreting the noise as valid logic level.

Successful reduction of inductive switching noise can be accomplished by
the following:

1. Reduce the number of outputs that switch simultaneously by dividinthem into groups with each group having a number of delay buffers inserted into their data paths
2. Reduce the effective power and ground pin inductance by assigning as many power and ground pads as possible