Low power design techniques

Why Low power in today's chip design ?

Dynamic power reduction techniques:

Power optimization techniques can be introduced at the RTL level.
This includes:

1. Clock gating
2. FSM encoding
3. Avoiding glitches or Deglitching
   
4. bus encoding

Clock gating:
We have many flip flops in our design.So there is clock transitioning continuously happening at the clock inputs of these flip flops.This contributes to dynamic power dissipation due to switching activity of the clock.
If the clock is gated and then sent to the flip flops , seems to reduce power dissipation than the one which is not gated.
The amount of power saving increases with increase in the number of registers.


FSM encoding:
Power reduction can be done at the algorithmic level by using proper encoding scheme for FSM state assignments.This depends on the transitions that take place while going from one state to next state.
Say from 3 to 4 in binary encoding scheme requires 3 transitions, while gray -code representation requires only one.
Less power is consumed when FSM state use gray-code encoding scheme.

Bus encoding:
Gray coding is also useful for power reduction n SOC bus interconnects.
Dynamic power in this case depends on the width of the bus and loading capacitance, so bus segmentation will naturally help in power reduction by reducing capacitance in bus segment.

In Bus, BI bus invert coding is implemented , where in it is decided whether to send actual data or its complement depending on the transitions on bus interconnect.This depends on the hamming distance between the present and the next state.If the hamming distance is greater than the half of width of the bus ,then next bus value is the complement of the next data of the bus.If the hamming distance is less than the half of the width of the bus , then the data sent is actual data.

Deglitching:
Power dissipation occurs due to the switching activity in cmos logic gates.Power can be saved significantly if the unnecessary switching can be avoided.Glitches are the unwanted momentary transitions that occur due to the delay in logic gates.
Glitches add to the number of transitions , they should be avoided.


The arithmetic operations are prone to produce glitches, if all the multiplies and adders are sequential and latches are not provided to hold their values until they become stable.Latches
hold the previous input value at each level thus avoiding glitches .
Another low power design technique is to replace flip flops with latches wherever possible.

Both latches and flip flops are building blocks of sequentialcircuits and their outputs depend on the current inputs as well as previous inputs and outputs.
The difference between latches and flip flop is that latches are level sensitive and flip flops are edge sensitive.
In D-latch, output Q obtain the value of the D-input at the specified level of the clock signal,it responds to the changes in the input as long as clock signal is asserted.
In D-flip-flop,output responds to changes in the input at the specified edges of the clock signal, thus preventing the output to respond to changes in the input after the rising or falling edge .The output of the flip flop remains constant even if the input changes after the rising or falling edge.


Multi-Threshold -
This techniques uses both low Vt and high Vt cells.Low -vt cells can be used in critical path while high -Vt cells off the critical path.This improves performance without increase in power.
The flip side of this technique that :
multi -vt cells causes fabrication complexity and increases design time.Improper optimization of the design may utilize more Low Vt cells and hence could end up with increased power.

Multi-Vdd (Voltage)
Power supply is directly proportional to dynamic power.Reducing voltage reduces dynamic power .But lower threshold voltage causes delay in the logic gates.Higher voltage can be applied to timing critical path and rest of the chip runs in lower voltage.Different blocks have different voltages which can be integrated in SOC. This increases power planning complexity in terms of laying down the power rails and power grid structure. Level shifters are necessary to interface between different blocks.


Power Gating:
Power gating is where the circuit blocks not in operation are temporarily turned off going to low power mode.And when they are required in operation, turned on to active mode.The goal of power gating is to reduce leakage power by temporarily turning off the circuit blocks and switching the two modes in a suitable manner so to reduce its impact on performance and maximize power performance.

It increases time delay as the gated modes should be safely entered and exited.