What is power budgeting?

Calculating the power dissipation at block level in the design will help us to know whether the design can meet the power specification and to estimate the size of the power grid needed in the floor plan.

Power planning

Why power planning is required?
To ensure that all the components in the chip have adequate power and ground connections.
Power network generally includes following things:
Power pad -to supply power to entire chip
power rings -run around the periphery of the die to supply power to standard cell 's core area, and individual hard macros.Rings are put in higher level routing layers so that lower level are used for signal routing.
Power rails-The horizontal wires are often referred as rails and vertical wires are called as straps.They run from end to end,crossing the entire die ,sections of the die.
Rails and straps are placed uniformly spaced array.Rails connect the power pins of the standard cell and extend to power rings,There they connect with vias.Widest trunks are put in higher level routing layers as with power rings.After the straps and trunks are inserted ,they are all well tied together using the vias and via stacks.

The uniformly spaced array of straps and rails may get modified to allow hard macro power rings , wiring keep out area and other restrictions.

Using lower level routing (typically metal1) ,rails are created only in standard cell placement areas that aren't already blocked by hard macros or wiring keep out.













There are two types of power planning and management.
1.core cell power
2.I/O cell power

In core cell power -VDD and VSS power rings are formed around the core and macro, depending on power requirement straps and trunks are created for the macros.

I/O cell power Power rings are formed around the I/O cell, and trunks are created connecting core power ring an power pad.
For Flattened design top to bottom approach is suitable..
For macros bottom to top approach is suitable.




Why power rings are made up of top metal layers?Why top metal layers should have low resistance and not lower metal layers?

R=rho*L/A;
Top metal layers have larger width than lower one.Lower metal layers are used for signal routing and to have adequate supply of power to all the components ,to decrease IR drop due to the resistance in the metal layers ,top metal layers are made wider,hence low resistance and are made up of copper .Lower metal layers are made up of aluminum.

Block Level floorplanning

Initial synthesis should be run to determine the total area of the cells in the block.
Determine area beyond the area of cells will depend on library,characteristics of design,technology.
It should be 70% utilization,An unusually high percentage of registers
or hard IP will increase this number; large numbers of multiplexers or other small, pin-dense cells will decrease it.

-Aspect Ratio
-Core Utilization
-shape of the block
-Location of pins
-power planning

Design implementation style

There are two styles of implementing a design:
a)Hierarchical
b)Flat
For small,medium ASIC ,flattening the design is more suited .
For very large concurrent ASIC,partitioning the design into sub design ,hierarchical is preferred.

In Flat implementation style , area usage is better since there is no need to reserve space around each sub partition for power,ground resources for routing.Timing analysis efficient since the entire design can be analyzed at once rather at the later stage after it is assembled.It has lot of information to store in memory space and run time increases rapidly with design size.
It has only leaf cells.

Hierarchical implementation style has blocks and sub -blocks.
The problem is the components in critical path may be sitting in different partitions which make critical path longer and also timing closure difficult,so it is necessary to generate timing constraints so that all the critical components are in the same partition closer to each other..It is used when there is need for substantial amount of data computing.It is done when sub circuit can be designed individually.

In this style design can be partitioned logically or physically.

Logical partition :design is partitioned depending on the logical functions, their inter connectivity with partitions and sub circuits.Each partition is place and routed separately is placed as macro or block at the top level ASIC.

Physical partition:
design is partitioned during physical design activity.Partitions can be a group of sub circuits combined , or a large circuit partitioned into small sub circuits.
Partitions are formed by recursively partitioning rectangular area having the design using horizontal and vertical lines.

Physical partitioning helps in minimizing delay (since each cluster will be subjected to constraints) satisfying design requirements in a small number of sub circuits.Initially,
these partitions have undefined dimensions and fixed area (i.e. the total area
of cells or instance added to the partition) with their associated ports, or
terminals, assigned to their boundaries such that the connectivity among
them is minimized. In order to place these partitions, or blocks, at the chip
level, their dimensions as well as their port placement must be defined.

ASIC hiearchy

what parameters differentiate between block and chip design?

Chip design has I/O pads and block has pins.
Chip design uses all the metal layers available,block may not use all the metal layers.
Chip design generally rectangular in shape,block can be in rectangle or rectilinear shape.
Chip design requires several packaging,block design ends in a macro.