Design implementation style

There are two styles of implementing a design:
a)Hierarchical
b)Flat
For small,medium ASIC ,flattening the design is more suited .
For very large concurrent ASIC,partitioning the design into sub design ,hierarchical is preferred.

In Flat implementation style , area usage is better since there is no need to reserve space around each sub partition for power,ground resources for routing.Timing analysis efficient since the entire design can be analyzed at once rather at the later stage after it is assembled.It has lot of information to store in memory space and run time increases rapidly with design size.
It has only leaf cells.

Hierarchical implementation style has blocks and sub -blocks.
The problem is the components in critical path may be sitting in different partitions which make critical path longer and also timing closure difficult,so it is necessary to generate timing constraints so that all the critical components are in the same partition closer to each other..It is used when there is need for substantial amount of data computing.It is done when sub circuit can be designed individually.

In this style design can be partitioned logically or physically.

Logical partition :design is partitioned depending on the logical functions, their inter connectivity with partitions and sub circuits.Each partition is place and routed separately is placed as macro or block at the top level ASIC.

Physical partition:
design is partitioned during physical design activity.Partitions can be a group of sub circuits combined , or a large circuit partitioned into small sub circuits.
Partitions are formed by recursively partitioning rectangular area having the design using horizontal and vertical lines.

Physical partitioning helps in minimizing delay (since each cluster will be subjected to constraints) satisfying design requirements in a small number of sub circuits.Initially,
these partitions have undefined dimensions and fixed area (i.e. the total area
of cells or instance added to the partition) with their associated ports, or
terminals, assigned to their boundaries such that the connectivity among
them is minimized. In order to place these partitions, or blocks, at the chip
level, their dimensions as well as their port placement must be defined.