Signal integrity issues and solutions

Signal integrity -is the quality of a signal on a line.Ignoring them can cause logic or timing problems leading to compromised performance or even component failures.
Following are the issues we would come across which would be considered while power planning.

1.Crosstalk
2.IR drop

Crosstalk is an unwanted signal on the victim line due to transmission line close to it.This happens due to coupling capacitance between them which are the function of separation between the lines and dielectric constant of the separated materials.
Crosstalk effects is function:
rise and fall edges on aggressor,
distance between the lines,
and the presence of signal reference planes.

Wires have capacitance to their adjacent neighbors and to the ground.

1.If wire A switches ,it brings with it along wire B due to capacitive coupling.
2.If wire A switches and wire B is supposed to switch simultaneously ,then it may cause switching delay.
3.If B is not supposed to switch then crosstalk introduces noise in B.

Crosstalk effect is larger is long wires , but it is negligible in short wires for large load,since load capacitance dominates.

Crosstalk delay effects:
The charge delivered to coupling capacitor is Q=Cadj.delta V.Delta V is change in voltage between A and B.
If A switches and B not switching then Delta V = Vdd.The total capacitance seen by A is coupling with B and wrt ground.
If A and B switch is the same direction, then delta V is zero,hence Cadj is completely absent.
If A and B switch in the opposite direction ,then delta V=2Vdd.So,twice as much charge is required,capacitance is twice as large switching through Vdd.
The crosstalk induces incremental delay on victim line,so delay is calculated due to crosstalk and then the length of the driven net is adjusted so that delay does not exceed a certain value.
Cross talk is in a sense treated as a delay by the router and the additional delay coming from cross coupled capacitance. When the nets are too close and run for a long
length in parallel the cross coupling cap is huge. To avoid this scenario make sure your routes don't run in parallel for a longer length.



Crosstalk Noise effects:If A switches and B is left floating then,B also partially switches due to noise introduced by A.
If B is driven then it opposes coupling ,so only small percentage of supply voltage will be the noise introduced in B.
During the noise event the aggressor transistor will be in saturation and victim is in linear region
For equal sized drivers,due to velocity saturation aggressor resistance will be twice to 4 times as larger than R victim.
It introduces noise glitches in victim net that might exceed the switching threshold of the receiving logic element.This effect is checked based on drive strength and relative position.the nets will be shortened and moved to reduce the crosstalk effects.






Solution:
1.increase the distance between them , coupling capacitance reduces which is straight forward solution.
2.Shielding victim from aggressor line is to put low impedance trace between lines.This way it provides path for the return current from signal line.
3.Another technique is wire re-ordering.In the original configuration,it may feel that the lines l1,l2,l3 are susceptible to crosstalk effects.
The transition on l2 is delayed due to opposing l1,while l2 induces downward transition on l3.But by reordering l2 and l3 , the transitions get canceled on l3.At the same time l2 is farther moved from l1 making it immune to the effects of l1.

Original


reorder










4.Microstrip and stripline architectures are used on high-speed PC boards to reduce the crosstalk between traces. These techniques pair a signal trace with a solid reference plane above or below it. The reference plane can be any DC voltage since crosstalk is an AC effect, so usually the planes are ground or one of the power supplies.
The low impedance reference plane captures the return current of the signal trace. This current creates a magnetic field that opposes the field in the signal trace, and creates an overall field that is confined locally and falls off rapidly with distance. Microstrip architecture has one reference plane while stripline has two, one on each side of the signal trace.









Since clock lines are spread throughout the chip, they can be victim to many aggressor lines, so special care must be taken. Long clock nets should be identified and isolated with either with spacing or shielding.

IR drop:
IR drop is occurs both in power and ground network due to the resistance in the metal layers.
narrower metal line width causes increase in resistance and hence IR drop.
The amount of voltage drop can be calculated as
deltaVdrop = Iavg *Reff
Reff-Effective resistance from power pads to logic gates.
Iavg -Average current switched by logic gates from the power lines coming from Vdd pad.










http://www.vlsitechnology.org/html/irdrop_1.html

Static IR drop:
refers to the drop due to current flow when the circuit is in the steady state,has no switching inputs.Steady-state IR drop is caused by the resistance of the metal wires comprising the power distribution network.

Dynamic IR drop:
refers to the voltage drop due to the current flow in the circuit which is switching,performing some function.Further, dynamic IR drop occurs when the simultaneous switching of on-chip components such as clocks, clocked elements, bus drivers and memory decoder drivers causes a dip or spike in the power/ground grid.

Dynamic IR drop is greater than static IR drop since the current flowing in the metal interconnect is greater than when the circuit is in a steady state.

IR drop effect:
IR drop reduces speed and noise immunity of the cells and macros.
First a reduced voltage difference between Vdd and Vss will reduce the cell's operating performance.If that cell is in the critical path,the decrease in cell performance will reduce the chip's operating frequency.IR drop reduces noise immunity and in extreme cases causes functional failure.


Methods to reduce IR drop:

1. Reduction in current consumption by logic gates .So low-power design techniques can be implemented.
2. widening the metal wires.widening the power lines and also adding more power lines.Extremely dense power lines are used in high performance chips.the wire resistance is proportional to the wire length from power pad to logic gates.
3. Increasing the number of Vdd and Vss pads in the chip to reduce current consumption for each pair of pads.
4. Spread the logic
5. If the gates along the metal line switch together ,then there is increase in IR drop,so some kind of switching order to be followed in case of larger current.
6. C4 technology can be used which provide area I/Os, that provide shorter power lines.
7. Clock gating reduces IR drop
8. Using low power cells.
9. Proper CTS structure-minimizing clock buffers in clock tree structure as they switch frequently.

what are low power cells. And how clock gating decrease IR drop. and how proper CTS structure will reduce IR drop specifically,, it reduces dynamic power.