Static dissipation due to:
1.sub threshold conduction while the transistor is OFF.
2.Tunneling current through gate oxide.
3Leakage current through reverse biased diodes.
Dynamic dissipation due to:
1.charging and discharging of input and load capacitance.
2.short circuit current while both PMOS and NMOS networks are ON.
Ptotal = Pstatic + Pdynamic
Let us see one by one:
Static power dissipation
Subthreshold Leakage:
The V-I characteristics of transistor shows that current Id flows only when gate to source voltage Vgs > Vt.But in reality when Vgs < Vt ,the transistor does not become OFF, there is some leakage,given by following expression.
Leakage = exp(-qVt/kT)
This happens due to carrier diffusion from source to drain in weak inversion.
So static power dissipation depend on temperature .So ,when chip heats up static power dissipation also exponentially increases.
Gate oxide tunneling:
When a high electric field is applied to gate oxide ,electrons may tunnel into gate oxide layer if it is less than 3-4nm thick which results in leakage.This leakage current exponentially depends on oxide thickness and Vdd.Electrons may tunnel into conduction band of the oxide layer.
There is finite probability that carriers may tunnel into gate oxide causing gate leakage current flowing into the gate.Junction Leakage:
There are many parasitic diodes which are formed for e.g, p-n junction between diffusion and substrate or well form diodes.To make these diodes reverse biased ,substrate is connected to GND and n-well to VDD .But these reverse biased diodes conduct a small amount of current.
Ireverse=A.Js.(e(q.Vbias/kT)-1)
Vbias-->reverse bias voltage across the junction
Js-->reverse satuartion current density
A-->junction area
Junction leakage is caused by diffusion and drift of minority carriers at the edges of depletion region and generation of electron -hole pair in the depletion region of the reverse biased junctions.
Dynamic Power Dissipation
Dynamic power dissipation occur when signal flow through CMOS logic circuit which change logic state.Power is drawn from power supply to charge the output node capacitance.
The output node capacitance consists of the following:
1.Output node capacitance of the logic gate:This is due to drain diffusion region.
2.Total interconnect capacitance.
3.Input node capacitance of the driven gate :This is due to the gate oxide capacitance.
Let us consider this inverter circuit .Power is consumed from the power supply to charge the output node capacitance. Power drawn from power supply is dissipated in PMOS during charge up and charge down process dissipates power in NMOS transistor.Only half of the power is stored as energy in capacitance,
Therefore energy stored in capacitor is= CL.VDD2 / 2.The other half is dissipated as heat in PMOS transistor.We see that energy dissipation in PMOS is independent of the size of PMOS.
This energy is then dissipated as heat in NMOS transistor.During discharge phase charge is removed from the capacitor and its energy is dissipated as heat in NMOS.
Each switching cycle takes a fixed amount of energy = CL. VDD2.
If a gate is switched on and off ‘fn’ times / second, then Pdynamic = CL. VDD2. fn.
Below mentioned steps can be taken to reduce dynamic power
1) Reduce power supply voltage Vdd
2) Reduce voltage swing in all nodes
3) Reduce the switching probability (transition factor)
4) Reduce load capacitance
Short Circuit Power:
The finite rise and fall time of the input to the CMOS logic gates causes a direct current path from VDD to Gnd,this exist for short duration during switching.
During switching both NMOS and PMOS are simultaneously turned ON,especially when the condition ,VTn < Vin < Vdd - |VTp| holds for the input voltage, where VTn and VTp are NMOS and PMOS thresholds, there will be a conductive path open between Vdd and GND because both the NMOS and PMOS devices will be simultaneously on.
When the input voltage exceeds threshold voltage VTn the NMOS starts conducting and until input voltage reaches Vdd-|Vtp| PMOS is ON.Thus for some time bot transistor are ON.Similar event causes short circuit current to flow when signal is falling.Short circuit current terminates when transition is completed.
short circuit current is directly dependent on rise time and fall time, reducing transition short circuit component decreases.But propagation delay need to be considered.
when input rise and fall time is greater than the output rise and fall time ,short circuit path will be for longer time ,so it is desirable to have equal rise and fall time edges.
also, if Vdd is less than the sum of Vtn and Vtp then short circuit current can be eliminated since there is no way that both transistor can be turned on for any input voltage.
