Latch-up is a condition in which parasitic components give rise to the low-resistance conducting path between the power rails i.e. vdd to Vss causing disastrous results.
Caused due to the glitches on power rails
How it works ?
Here image shows the key parasitic components associated with a p-well structure.
In effect, 2 transistors and 2 resistance forms a path between Vdd and Vss. If sufficient subrate current flows to generate enough volatge across substarte resistance Rs to turn on transistor T1, this will then draw current through pwell resistance Rp and if the voltage developed is sufficient then transistor T2 turns on establishing low-resistance oath between the supply rails. If current gain of the 2 transistor are such that b1xb2>1 then latch may occur.
How to avoid latch up ?
Introduction of gaurd rings
Increase in sub doping which inturn decreases value of Rs
Rp can be reduced by control of fabrication parameters ensuring low contact resistance to Vss
http://cnx.org/content/m1031/latest/
Caused due to the glitches on power rails
How it works ?
Here image shows the key parasitic components associated with a p-well structure.
In effect, 2 transistors and 2 resistance forms a path between Vdd and Vss. If sufficient subrate current flows to generate enough volatge across substarte resistance Rs to turn on transistor T1, this will then draw current through pwell resistance Rp and if the voltage developed is sufficient then transistor T2 turns on establishing low-resistance oath between the supply rails. If current gain of the 2 transistor are such that b1xb2>1 then latch may occur.
How to avoid latch up ?
Introduction of gaurd rings
Increase in sub doping which inturn decreases value of Rs
Rp can be reduced by control of fabrication parameters ensuring low contact resistance to Vss
http://cnx.org/content/m1031/latest/
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