standard cell delay

The propagation delay in a standard cell is given by average of two time intervals.


tp = (th+ tr)/2

Propagation delay is the time difference between approximately 50% of the input transition and 50% of the output transition.

If the input waveform changes from zero to supply voltage (VDD) or from supply
voltage (VDD) to zero value, then low-to-high and high-to-low propagation
delays can be expressed as
tplh = ClVdd/(beta)p(Vdd-|vtp|)2
tphl = clVdd/(beta)p(Vdd - |vtn|)2

to improve the propagation delay of a given standard cell, one could
Increase supply voltage,
Reduce threshold voltage,
Increase transistors gain factors, or
Reduce the load capacitance.

Reducing load capacitance and increasing supply voltage is outside the standard cell.
Reduction of threshold voltage depends on semiconductor foundry and is part of the standard cell characterization.The only available parameter to the circuit designer is to increase gain factor.

the length and width of the transistor are related to gain factor beta.

In Wp/Wn ratio determination, it is desired to set

betan = k betap.
Wp/Wn = 2/k

In the ideal situation, k is equal to 1. This means that for a CMOS inverter to
charge and discharge capacitive loads in the same amount of time, the
channel width of the PMOS transistor must be twice as large as the channel
width of the NMOS transistor.

Although increasing the value of Wp / Wn reduces the cell propagation
delay, it also increases the active area capacitance and gate capacitance. This
increase in capacitance adversely affects the gate speed. Therefore, circuit
designers must make a trade off in determining how large the transistors
should be such that their propagation delays are optimal.

Fast circuits consume more area than slow circuits.