The propagation delay in a standard cell is given by average of two time intervals.
tp = (th+ tr)/2
Propagation delay is the time difference between approximately 50% of the input transition and 50% of the output transition.
If the input waveform changes from zero to supply voltage (VDD) or from supply
voltage (VDD) to zero value, then low-to-high and high-to-low propagation
delays can be expressed as
tplh = ClVdd/(beta)p(Vdd-|vtp|)2
tphl = clVdd/(beta)p(Vdd - |vtn|)2
to improve the propagation delay of a given standard cell, one could
Increase supply voltage,
Reduce threshold voltage,
Increase transistors gain factors, or
Reduce the load capacitance.
Reducing load capacitance and increasing supply voltage is outside the standard cell.
Reduction of threshold voltage depends on semiconductor foundry and is part of the standard cell characterization.The only available parameter to the circuit designer is to increase gain factor.
the length and width of the transistor are related to gain factor beta.
In Wp/Wn ratio determination, it is desired to set
betan = k betap.
Wp/Wn = 2/k
In the ideal situation, k is equal to 1. This means that for a CMOS inverter to
charge and discharge capacitive loads in the same amount of time, the
channel width of the PMOS transistor must be twice as large as the channel
width of the NMOS transistor.
Although increasing the value of Wp / Wn reduces the cell propagation
delay, it also increases the active area capacitance and gate capacitance. This
increase in capacitance adversely affects the gate speed. Therefore, circuit
designers must make a trade off in determining how large the transistors
should be such that their propagation delays are optimal.
Fast circuits consume more area than slow circuits.
Friday, April 23, 2010
Steps in Placement
Detach Scan chain and Scan chain reordering:
what is a scan chain?
Scan chain is one of the DFT strategies to improve chip's observability and controllability.It is collection of flip flops connected by scan chain.In the chain the output of the previous flip flop is
connected to the scan data input of the next flip flop.The data is sent to scan input and output of the logic operation is observed at the scan output.The nodes along the scan chain can be set to intended value 0 or 1 by the scan chain.The effect of these settings can be seen by shifting the data through out the scan chain, controlled and observed.
Physical wire connection between adjacent flip flops depends on the logical order of the chain.Logical proximity does not match with physical proximity.
Logical order is decided during logic synthesis stage through the random process or alphabetical order since physical locations are unknown at that time.
As a result if the original chains are retained, then routing,physical wire connections will not be optimized.
Best approach is to disconnect the scan chain before placement , so that the normal placement will not be disturbed by the connectivity of the scan chains.Then reorder the chain arrangement after the placement step after all the physical locations are fixed and known.The reordering based on physical location information improves overall routability and total connecting wire length.
All WLM (wire load models ) are removed before performing timing optimization and timing is calculated based on VR virtual route.Virtual route is the shortest Manhattan distance between two pins.
Manhattan right angle ruler for backend.It is also called as city-block distance. It is so named because it is the distance a car would drive in a city laid out in square blocks, like Manhattan (discounting the facts that in Manhattan there are one-way and oblique streets and that real streets only exist at the edges of blocks - there is no 3.14th Avenue). Any route from a corner to another one that is 3 blocks East and 6 blocks North, will cover at least 9 blocks.
The distance between the two points measured along axes at right angles.
Set Placement and timing options:
No cells under the preroute of the metal layer and under the via selected.
P & R tool prevents pins of standard cells from being placed under the metal layers you specify. This means that a standard is not be placed in a location when any pin of the cell overlaps with a preroute of the metal layer. For example, if M3 is selected, a standard cell will not be placed when any of its pins (regardless of the pin’s metal layer) overlaps with a preroute on M3.
Avoiding pin overlap with preroutes improves routability because there are less routing resources under preroutes due to the preroute and any vias and contacts along the preroutes.
Placement optimization:
PrePlace optimization:
Post Placement optimization before CTS:
Effect of CTS:
Worst negative slack corresponds to the path having maximum negative slack.
Total negative slack is the summation of all WNS per end point.
When TNS >> WNS, there might be sub critical path violations which are as good as the critical path violations.
Optimization during placement mainly works on the critical path of each clock domain and stops when it cannot further improve timing.
Critical range optimization works on sub -critical paths to reduce TNS and the total number of violation paths.
Iterate Post placement optimization and critical range optimization until remaining violations are acceptably small and if further improvement are seen.
Timing Driven Placement
P & R tool requires timing constraints to understand design timing objectives.The most standard
timing constraints on most designs include arrival times of the input signals to the design as well as the required arrival time at the output of the chip.This also include clock period of the system clock and as well as other clocks if the design contains multiple clock domains.
The timing information that tool uses is based upon the standard cell delays and wire connected to all these cells in the design.
The standard cell delays are the function of input transition and as well as the summation of capacitance of output wire and input gates of all the logic connected to the output wire.
Wire delays are the function of resistance of the metal layers and summation of wire capacitance and input gate capacitance.
Timing driven placement is the process of placing the standard cells in the rows of the core area using timing constraints as the guidelines as to where to place the cells.
Evaluation of Placement:
After performing automatic placement, evaluate the placement and make changes to improve the routability of the design.
During placement, tool calculates routing congestion, based on the availability of wire tracks inside the global routing cells. Using these routing congestion calculations, It produces a placement congestion map that shows the estimated amount of routing congestion within the design.
what is a scan chain?
Scan chain is one of the DFT strategies to improve chip's observability and controllability.It is collection of flip flops connected by scan chain.In the chain the output of the previous flip flop is
connected to the scan data input of the next flip flop.The data is sent to scan input and output of the logic operation is observed at the scan output.The nodes along the scan chain can be set to intended value 0 or 1 by the scan chain.The effect of these settings can be seen by shifting the data through out the scan chain, controlled and observed.
Physical wire connection between adjacent flip flops depends on the logical order of the chain.Logical proximity does not match with physical proximity.
Logical order is decided during logic synthesis stage through the random process or alphabetical order since physical locations are unknown at that time.
As a result if the original chains are retained, then routing,physical wire connections will not be optimized.
Best approach is to disconnect the scan chain before placement , so that the normal placement will not be disturbed by the connectivity of the scan chains.Then reorder the chain arrangement after the placement step after all the physical locations are fixed and known.The reordering based on physical location information improves overall routability and total connecting wire length.
All WLM (wire load models ) are removed before performing timing optimization and timing is calculated based on VR virtual route.Virtual route is the shortest Manhattan distance between two pins.
Manhattan right angle ruler for backend.It is also called as city-block distance. It is so named because it is the distance a car would drive in a city laid out in square blocks, like Manhattan (discounting the facts that in Manhattan there are one-way and oblique streets and that real streets only exist at the edges of blocks - there is no 3.14th Avenue). Any route from a corner to another one that is 3 blocks East and 6 blocks North, will cover at least 9 blocks.
The distance between the two points measured along axes at right angles.
Set Placement and timing options:
No cells under the preroute of the metal layer and under the via selected.
P & R tool prevents pins of standard cells from being placed under the metal layers you specify. This means that a standard is not be placed in a location when any pin of the cell overlaps with a preroute of the metal layer. For example, if M3 is selected, a standard cell will not be placed when any of its pins (regardless of the pin’s metal layer) overlaps with a preroute on M3.
Avoiding pin overlap with preroutes improves routability because there are less routing resources under preroutes due to the preroute and any vias and contacts along the preroutes.
Placement optimization:
PrePlace optimization:
- It generates the initial placement before optimizing the netlist to get the wiring information.
- It collapses non-critical buffer, reduces total cell area by downsizing so that the netlist is easier to place.
- High fanout nets contain significantly large number of buffers which can impact placement so,instead of minimizing the buffer , it rebuilds the HFN nets based on more accurate RC estimates.
- Performs quick logic synthesis.
- Places all the standard cells.
- It re-optimizes the logic based on virtual route.It does cell sizing,area recovery, gate duplication,buffer insertion,net splitting.Optimizes the gates for setup timing based on virtual route.
- incremental timing, and congestion-driven placement.
Post Placement optimization before CTS:
- Optimization is done with ideal clocks.
- It performs a more specific timing optimization of the netlist and the layout, including quick fixing of setup and hold violations and maximum transition and maximum capacitance violations by buffering the gates.
- It can do placement optimization based on global routing.
Effect of CTS:
- Clock buffers are added.
- Congestion may increase.
- Non clock tree cells may have been moved to less ideal locations.
- Can introduce new timing and max tran/cap violation.
- Post-placement optimization after clock tree synthesis improves the timing results of your design with propagated clocks. It takes the clock tree into account so that the clock skew can be preserved. Post-placement optimization after clock tree synthesis has an option to perform congestion removal before running optimization
- Perform logical and placement optimization to fix timing and max cap/tran violation.
- Fixing hold time is recommended here.
- Reduce congestion by removing unnecessary non-clock tree buffers.
Worst negative slack corresponds to the path having maximum negative slack.
Total negative slack is the summation of all WNS per end point.
When TNS >> WNS, there might be sub critical path violations which are as good as the critical path violations.
Optimization during placement mainly works on the critical path of each clock domain and stops when it cannot further improve timing.
Critical range optimization works on sub -critical paths to reduce TNS and the total number of violation paths.
Iterate Post placement optimization and critical range optimization until remaining violations are acceptably small and if further improvement are seen.
Timing Driven Placement
P & R tool requires timing constraints to understand design timing objectives.The most standard
timing constraints on most designs include arrival times of the input signals to the design as well as the required arrival time at the output of the chip.This also include clock period of the system clock and as well as other clocks if the design contains multiple clock domains.
The timing information that tool uses is based upon the standard cell delays and wire connected to all these cells in the design.
The standard cell delays are the function of input transition and as well as the summation of capacitance of output wire and input gates of all the logic connected to the output wire.
Wire delays are the function of resistance of the metal layers and summation of wire capacitance and input gate capacitance.
Timing driven placement is the process of placing the standard cells in the rows of the core area using timing constraints as the guidelines as to where to place the cells.
Evaluation of Placement:
After performing automatic placement, evaluate the placement and make changes to improve the routability of the design.
During placement, tool calculates routing congestion, based on the availability of wire tracks inside the global routing cells. Using these routing congestion calculations, It produces a placement congestion map that shows the estimated amount of routing congestion within the design.
Thursday, April 22, 2010
Placement objectives
what is Placement?
Placement is process of placing the cells,searching for appropriate place within the floorplan of the chip for each cell in the netlist.
Placement objectives:
-Guarantee the router can complete routing step
-minimize critical net delay
-make the chip as dense as possible.
Placement additional objectives are as follows:
Minimize the estimated interconnect length.
Meet the timing requirements for the critical nets
Minimize interconnect congestion
Placement is process of placing the cells,searching for appropriate place within the floorplan of the chip for each cell in the netlist.
Placement objectives:
-Guarantee the router can complete routing step
-minimize critical net delay
-make the chip as dense as possible.
Placement additional objectives are as follows:
Minimize the estimated interconnect length.
Meet the timing requirements for the critical nets
Minimize interconnect congestion
Channel definition and Slicing Floor Plan
During the floor plan we assign the areas between the blocks for interconnect.This is called channel definition or channel allocation
T-shaped junction between two rectangular channels
Routing a T-junction between two channels in two-level metal. The dots represent logic cell pins. (a) Routing channel A (the stem of the T) first allows us to adjust the width of channel B. (b) If we route channel B first (the top of the T), this fixes the width of channel A. We have to route the stem of a T-junction before we route the top.
Channel ordering:
Choosing the order of rectangular channel to route is channel ordering.
Slicing Floor Plan:
Suppose a chip has several blocks.We cut along the block boundaries in the chip into two pieces.
And we continue in the same manner until we separate all the blocks is called slicing floorplan.
Defining the channel routing order for a slicing floorplan using a slicing tree. (a) Make a cut all the way across the chip between circuit blocks. Continue slicing until each piece contains just one circuit block. Each cut divides a piece into two without cutting through a circuit block. (b) A sequence of cuts: 1, 2, 3, and 4 that successively slices the chip until only circuit blocks are left. (c) The slicing tree corresponding to the sequence of cuts gives the order in which to route the channels: 4, 3, 2, and finally 1.
It shows how the sequence we use to slice the chip defines a hierarchy of the blocks. Reversing the slicing order ensures that we route the stems of all the channel T-junctions first.
Cyclic constraint and non-slicing floorplan:
Non -slicing floor plan is the one where we cannot cut the chip into pieces without chopping a circuit block into two.We cannot route a channel until other channels are routed.This is called cyclic constraint.
The only solution to remove the cyclic constraint is to move the block, but this will make it area inefficient,routing difficult.We may have to use area based router or L-shaped or switch boxes(fixed connectors) for routing.
Channel definition and ordering. (a) We can eliminate the cyclic constraint by merging the blocks A and C. (b) A slicing structure.
We can also merge circuit blocks since it is more efficient to route the row -based block by flattening them than route between the blocks.Now , we get a slicing floorplan .Fig(b) shows the channel definition and routing order for our chip.
T-shaped junction between two rectangular channels
Routing a T-junction between two channels in two-level metal. The dots represent logic cell pins. (a) Routing channel A (the stem of the T) first allows us to adjust the width of channel B. (b) If we route channel B first (the top of the T), this fixes the width of channel A. We have to route the stem of a T-junction before we route the top.
Channel ordering:
Choosing the order of rectangular channel to route is channel ordering.
Slicing Floor Plan:
Suppose a chip has several blocks.We cut along the block boundaries in the chip into two pieces.
And we continue in the same manner until we separate all the blocks is called slicing floorplan.
Defining the channel routing order for a slicing floorplan using a slicing tree. (a) Make a cut all the way across the chip between circuit blocks. Continue slicing until each piece contains just one circuit block. Each cut divides a piece into two without cutting through a circuit block. (b) A sequence of cuts: 1, 2, 3, and 4 that successively slices the chip until only circuit blocks are left. (c) The slicing tree corresponding to the sequence of cuts gives the order in which to route the channels: 4, 3, 2, and finally 1.
It shows how the sequence we use to slice the chip defines a hierarchy of the blocks. Reversing the slicing order ensures that we route the stems of all the channel T-junctions first.
Cyclic constraint and non-slicing floorplan:
Non -slicing floor plan is the one where we cannot cut the chip into pieces without chopping a circuit block into two.We cannot route a channel until other channels are routed.This is called cyclic constraint.
The only solution to remove the cyclic constraint is to move the block, but this will make it area inefficient,routing difficult.We may have to use area based router or L-shaped or switch boxes(fixed connectors) for routing.
Channel definition and ordering. (a) We can eliminate the cyclic constraint by merging the blocks A and C. (b) A slicing structure.
We can also merge circuit blocks since it is more efficient to route the row -based block by flattening them than route between the blocks.Now , we get a slicing floorplan .Fig(b) shows the channel definition and routing order for our chip.
Tuesday, April 20, 2010
Goal and objectives of the Floor plan and its Evaluation
The goals of floor planning are to:
The percentage of core utilized by placed standard cell and macros.
Determines die size:
Core limited :Core logic determines the die size.
Pad limited :No of I/O pads determines the die size.Pad area is more than cell area.
We need to control the aspect ratio of our floor plan because we have to fit our chip into the die cavity (a fixed-size hole, usually square) inside a package
Evaluation of Floorplan
-a through away placement
-Estimate global route congestion
- defining the core area, aspect ratio .
- arrange the blocks on a chip.
- decide the location of the I/O pads.
- decide the location and number of the power pads.
- decide the type of power distribution
Floor planning control parameters like aspect ratio, core utilization are defined as follows:
Aspect Ratio =W/L
The percentage of core utilized by placed standard cell and macros.
Determines die size:
Core limited :Core logic determines the die size.
Pad limited :No of I/O pads determines the die size.Pad area is more than cell area.
We need to control the aspect ratio of our floor plan because we have to fit our chip into the die cavity (a fixed-size hole, usually square) inside a package
Evaluation of Floorplan
-a through away placement
-Estimate global route congestion
Monday, April 19, 2010
I/O Pad Placement
There are three types of I/O pads:
Electromigration:
It is the movement of molecular atoms from one are to another area caused by excessive flowof current in the direction of flow of electrons.It results in shorts between electric wires, hillocks, high metal resistance causing ASIC failure.
No of pads can be determined by Ngnd = Itotal/Imax
Ngnd -No of ground pads
Itotal -ASIC total current
Imax -Maximum EM current in amperes /ground pad.
Switching noise:
switching noise is generated when ASIC output make transitions from one state to another.
Insufficient ground and power pads may lead to data errors due to switching noise transitions.
1.Capacitive coupling
dv/dt
It is the disturbance caused in adjacent package pin when switching transients inject pulses via parasitic capacitive coupling.
This can be reduced by:
1.Isolate sensitive clock inputs pin from the switching signal pads.
2.Group bidirectional pads together so that all are in either input or output mode.
2.Inductive coupling
Simultaneous switching of the ASIC output induces rapid current changes in power and ground busses.The inductance in power and ground pins causes voltage fluctuations in internal ASIC power and ground level.
The rapid current changes may induce logic error or may cause noise spikes on non-switching output pads that affect signals connected to other systems.
The maximum L (di/dt) occurs when ASIC output make a transition to another voltage level and
absolute current increases from zero through a wire of inductance L.Factors such as process, ambient temperature, voltage, location of output pads, and number of simultaneous
switching output pads determine the magnitude of inductive switching noise.
To control inductive switching noise, enough power and ground pads mustbe assigned and placed correctly. This way the noise magnitude will be limited. This noise reduction will prevent inputs of ASIC design from interpreting the noise as valid logic level.
Successful reduction of inductive switching noise can be accomplished by
the following:
- Power
- Ground
- Signal
Electromigration:
It is the movement of molecular atoms from one are to another area caused by excessive flowof current in the direction of flow of electrons.It results in shorts between electric wires, hillocks, high metal resistance causing ASIC failure.
No of pads can be determined by Ngnd = Itotal/Imax
Ngnd -No of ground pads
Itotal -ASIC total current
Imax -Maximum EM current in amperes /ground pad.
Switching noise:
switching noise is generated when ASIC output make transitions from one state to another.
Insufficient ground and power pads may lead to data errors due to switching noise transitions.
1.Capacitive coupling
dv/dt
It is the disturbance caused in adjacent package pin when switching transients inject pulses via parasitic capacitive coupling.
This can be reduced by:
1.Isolate sensitive clock inputs pin from the switching signal pads.
2.Group bidirectional pads together so that all are in either input or output mode.
2.Inductive coupling
Simultaneous switching of the ASIC output induces rapid current changes in power and ground busses.The inductance in power and ground pins causes voltage fluctuations in internal ASIC power and ground level.
The rapid current changes may induce logic error or may cause noise spikes on non-switching output pads that affect signals connected to other systems.
The maximum L (di/dt) occurs when ASIC output make a transition to another voltage level and
absolute current increases from zero through a wire of inductance L.Factors such as process, ambient temperature, voltage, location of output pads, and number of simultaneous
switching output pads determine the magnitude of inductive switching noise.
To control inductive switching noise, enough power and ground pads mustbe assigned and placed correctly. This way the noise magnitude will be limited. This noise reduction will prevent inputs of ASIC design from interpreting the noise as valid logic level.
Successful reduction of inductive switching noise can be accomplished by
the following:
- Reduce the number of outputs that switch simultaneously by dividinthem into groups with each group having a number of delay buffers inserted into their data paths
- Reduce the effective power and ground pin inductance by assigning as many power and ground pads as possible
Sunday, April 18, 2010
Macro Placement
Macro placement takes place after I/O placement.Macro placement can be done manually or automated.
The physical measure of the quality of placement of macros can be as follows:
1.wire length
2.data flow
3.port accessibility
4.timing
Placement of the macro should not lead to segmented floor plan.In a segmented floor plan , standard cells area is not continuous.There is excessive interconnections between the standard cells located at the bottom of the die to those located at the top.This leads to increase in wire length.
To avoid segmentation , macro should be placed such that standard cell area is continuous.Macros could be kept along the ASIC core area.
Segmented Floor Plan
There can be increase in wire length due to the orientation of macro placement and pin locations, to nets being connected may be of different length.Macros should be placed accordingly so that their ports are facing the core area or to the standard cells, orientation should match available routing layers.
Floor plan with Macros Facing Standard Cells Region.
Placement of macro relative to standard cell placement and macro port accessibility has an impact on chip's final routing.The global router gives a statistical and graphical report on the analysis of routing congestion.
Routing congestion is caused by not enough space to provide routing channels between the macros for I/O connection and macro;routing is prohibited and standard cells trap pockets at the edges of the macros or within the corners of the floor plan.
Standard cell trap pockets are long, thin channels between macros.If there are more cells in the channel then it may cause routing congestion.Therefore,these channels need to be kept free for most standard cells and should be available for repeater or buffer insertion
Floor plan with Standard Cells Trap Pocket
Blockage layers:
Most Physical designs require keep-out regions or buffer only which is defined by blockage layer ,which refrain placer from moving the standard cells into this region.
Blockage layers avoid routing congestion.Suppose a macro blocks routing layers and then wire try to detour along the corners of the macros causing congestion at the corners.Blockage layer can be placed at the corners of the macros to reserve resources for the router.These are placed over pre-placed macros covering the power and ground rings.
Naturally, the wires that are used in keep-out regions have a tendency to be long. By allowing buffer insertion in those areas by using a buffer-only region (or blockage), the placer will taper these long nets and thus avoid the long transition times associated with them.
Fly lines:
After macro placement and standard cells are placed , connectivity analysis is performed.This is done by the fly lines.This is to study the connections between i/o pads,macros, standard cells.One can identify seeing the fly lines that whether moving or rotating the macros can reduce wire length which improve routability during floor planning stage.
The physical measure of the quality of placement of macros can be as follows:
1.wire length
2.data flow
3.port accessibility
4.timing
Placement of the macro should not lead to segmented floor plan.In a segmented floor plan , standard cells area is not continuous.There is excessive interconnections between the standard cells located at the bottom of the die to those located at the top.This leads to increase in wire length.
To avoid segmentation , macro should be placed such that standard cell area is continuous.Macros could be kept along the ASIC core area.
Segmented Floor Plan
There can be increase in wire length due to the orientation of macro placement and pin locations, to nets being connected may be of different length.Macros should be placed accordingly so that their ports are facing the core area or to the standard cells, orientation should match available routing layers.
Floor plan with Macros Facing Standard Cells Region.
Placement of macro relative to standard cell placement and macro port accessibility has an impact on chip's final routing.The global router gives a statistical and graphical report on the analysis of routing congestion.
Routing congestion is caused by not enough space to provide routing channels between the macros for I/O connection and macro;routing is prohibited and standard cells trap pockets at the edges of the macros or within the corners of the floor plan.
Standard cell trap pockets are long, thin channels between macros.If there are more cells in the channel then it may cause routing congestion.Therefore,these channels need to be kept free for most standard cells and should be available for repeater or buffer insertion
Floor plan with Standard Cells Trap Pocket
Blockage layers:
Most Physical designs require keep-out regions or buffer only which is defined by blockage layer ,which refrain placer from moving the standard cells into this region.
Blockage layers avoid routing congestion.Suppose a macro blocks routing layers and then wire try to detour along the corners of the macros causing congestion at the corners.Blockage layer can be placed at the corners of the macros to reserve resources for the router.These are placed over pre-placed macros covering the power and ground rings.
Naturally, the wires that are used in keep-out regions have a tendency to be long. By allowing buffer insertion in those areas by using a buffer-only region (or blockage), the placer will taper these long nets and thus avoid the long transition times associated with them.
Fly lines:
After macro placement and standard cells are placed , connectivity analysis is performed.This is done by the fly lines.This is to study the connections between i/o pads,macros, standard cells.One can identify seeing the fly lines that whether moving or rotating the macros can reduce wire length which improve routability during floor planning stage.
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