what is Placement?
Placement is process of placing the cells,searching for appropriate place within the floorplan of the chip for each cell in the netlist.
Placement objectives:
-Guarantee the router can complete routing step
-minimize critical net delay
-make the chip as dense as possible.
Placement additional objectives are as follows:
Minimize the estimated interconnect length.
Meet the timing requirements for the critical nets
Minimize interconnect congestion
Thursday, April 22, 2010
Channel definition and Slicing Floor Plan
During the floor plan we assign the areas between the blocks for interconnect.This is called channel definition or channel allocation
T-shaped junction between two rectangular channels
Routing a T-junction between two channels in two-level metal. The dots represent logic cell pins. (a) Routing channel A (the stem of the T) first allows us to adjust the width of channel B. (b) If we route channel B first (the top of the T), this fixes the width of channel A. We have to route the stem of a T-junction before we route the top.
Channel ordering:
Choosing the order of rectangular channel to route is channel ordering.
Slicing Floor Plan:
Suppose a chip has several blocks.We cut along the block boundaries in the chip into two pieces.
And we continue in the same manner until we separate all the blocks is called slicing floorplan.
Defining the channel routing order for a slicing floorplan using a slicing tree. (a) Make a cut all the way across the chip between circuit blocks. Continue slicing until each piece contains just one circuit block. Each cut divides a piece into two without cutting through a circuit block. (b) A sequence of cuts: 1, 2, 3, and 4 that successively slices the chip until only circuit blocks are left. (c) The slicing tree corresponding to the sequence of cuts gives the order in which to route the channels: 4, 3, 2, and finally 1.
It shows how the sequence we use to slice the chip defines a hierarchy of the blocks. Reversing the slicing order ensures that we route the stems of all the channel T-junctions first.
Cyclic constraint and non-slicing floorplan:
Non -slicing floor plan is the one where we cannot cut the chip into pieces without chopping a circuit block into two.We cannot route a channel until other channels are routed.This is called cyclic constraint.
The only solution to remove the cyclic constraint is to move the block, but this will make it area inefficient,routing difficult.We may have to use area based router or L-shaped or switch boxes(fixed connectors) for routing.
Channel definition and ordering. (a) We can eliminate the cyclic constraint by merging the blocks A and C. (b) A slicing structure.
We can also merge circuit blocks since it is more efficient to route the row -based block by flattening them than route between the blocks.Now , we get a slicing floorplan .Fig(b) shows the channel definition and routing order for our chip.
T-shaped junction between two rectangular channels
Routing a T-junction between two channels in two-level metal. The dots represent logic cell pins. (a) Routing channel A (the stem of the T) first allows us to adjust the width of channel B. (b) If we route channel B first (the top of the T), this fixes the width of channel A. We have to route the stem of a T-junction before we route the top.
Channel ordering:
Choosing the order of rectangular channel to route is channel ordering.
Slicing Floor Plan:
Suppose a chip has several blocks.We cut along the block boundaries in the chip into two pieces.
And we continue in the same manner until we separate all the blocks is called slicing floorplan.
Defining the channel routing order for a slicing floorplan using a slicing tree. (a) Make a cut all the way across the chip between circuit blocks. Continue slicing until each piece contains just one circuit block. Each cut divides a piece into two without cutting through a circuit block. (b) A sequence of cuts: 1, 2, 3, and 4 that successively slices the chip until only circuit blocks are left. (c) The slicing tree corresponding to the sequence of cuts gives the order in which to route the channels: 4, 3, 2, and finally 1.
It shows how the sequence we use to slice the chip defines a hierarchy of the blocks. Reversing the slicing order ensures that we route the stems of all the channel T-junctions first.
Cyclic constraint and non-slicing floorplan:
Non -slicing floor plan is the one where we cannot cut the chip into pieces without chopping a circuit block into two.We cannot route a channel until other channels are routed.This is called cyclic constraint.
The only solution to remove the cyclic constraint is to move the block, but this will make it area inefficient,routing difficult.We may have to use area based router or L-shaped or switch boxes(fixed connectors) for routing.
Channel definition and ordering. (a) We can eliminate the cyclic constraint by merging the blocks A and C. (b) A slicing structure.
We can also merge circuit blocks since it is more efficient to route the row -based block by flattening them than route between the blocks.Now , we get a slicing floorplan .Fig(b) shows the channel definition and routing order for our chip.
Tuesday, April 20, 2010
Goal and objectives of the Floor plan and its Evaluation
The goals of floor planning are to:
The percentage of core utilized by placed standard cell and macros.
Determines die size:
Core limited :Core logic determines the die size.
Pad limited :No of I/O pads determines the die size.Pad area is more than cell area.
We need to control the aspect ratio of our floor plan because we have to fit our chip into the die cavity (a fixed-size hole, usually square) inside a package
Evaluation of Floorplan
-a through away placement
-Estimate global route congestion
- defining the core area, aspect ratio .
- arrange the blocks on a chip.
- decide the location of the I/O pads.
- decide the location and number of the power pads.
- decide the type of power distribution
Floor planning control parameters like aspect ratio, core utilization are defined as follows:
Aspect Ratio =W/L
The percentage of core utilized by placed standard cell and macros.
Determines die size:
Core limited :Core logic determines the die size.
Pad limited :No of I/O pads determines the die size.Pad area is more than cell area.
We need to control the aspect ratio of our floor plan because we have to fit our chip into the die cavity (a fixed-size hole, usually square) inside a package
Evaluation of Floorplan
-a through away placement
-Estimate global route congestion
Monday, April 19, 2010
I/O Pad Placement
There are three types of I/O pads:
Electromigration:
It is the movement of molecular atoms from one are to another area caused by excessive flowof current in the direction of flow of electrons.It results in shorts between electric wires, hillocks, high metal resistance causing ASIC failure.
No of pads can be determined by Ngnd = Itotal/Imax
Ngnd -No of ground pads
Itotal -ASIC total current
Imax -Maximum EM current in amperes /ground pad.
Switching noise:
switching noise is generated when ASIC output make transitions from one state to another.
Insufficient ground and power pads may lead to data errors due to switching noise transitions.
1.Capacitive coupling
dv/dt
It is the disturbance caused in adjacent package pin when switching transients inject pulses via parasitic capacitive coupling.
This can be reduced by:
1.Isolate sensitive clock inputs pin from the switching signal pads.
2.Group bidirectional pads together so that all are in either input or output mode.
2.Inductive coupling
Simultaneous switching of the ASIC output induces rapid current changes in power and ground busses.The inductance in power and ground pins causes voltage fluctuations in internal ASIC power and ground level.
The rapid current changes may induce logic error or may cause noise spikes on non-switching output pads that affect signals connected to other systems.
The maximum L (di/dt) occurs when ASIC output make a transition to another voltage level and
absolute current increases from zero through a wire of inductance L.Factors such as process, ambient temperature, voltage, location of output pads, and number of simultaneous
switching output pads determine the magnitude of inductive switching noise.
To control inductive switching noise, enough power and ground pads mustbe assigned and placed correctly. This way the noise magnitude will be limited. This noise reduction will prevent inputs of ASIC design from interpreting the noise as valid logic level.
Successful reduction of inductive switching noise can be accomplished by
the following:
- Power
- Ground
- Signal
Electromigration:
It is the movement of molecular atoms from one are to another area caused by excessive flowof current in the direction of flow of electrons.It results in shorts between electric wires, hillocks, high metal resistance causing ASIC failure.
No of pads can be determined by Ngnd = Itotal/Imax
Ngnd -No of ground pads
Itotal -ASIC total current
Imax -Maximum EM current in amperes /ground pad.
Switching noise:
switching noise is generated when ASIC output make transitions from one state to another.
Insufficient ground and power pads may lead to data errors due to switching noise transitions.
1.Capacitive coupling
dv/dt
It is the disturbance caused in adjacent package pin when switching transients inject pulses via parasitic capacitive coupling.
This can be reduced by:
1.Isolate sensitive clock inputs pin from the switching signal pads.
2.Group bidirectional pads together so that all are in either input or output mode.
2.Inductive coupling
Simultaneous switching of the ASIC output induces rapid current changes in power and ground busses.The inductance in power and ground pins causes voltage fluctuations in internal ASIC power and ground level.
The rapid current changes may induce logic error or may cause noise spikes on non-switching output pads that affect signals connected to other systems.
The maximum L (di/dt) occurs when ASIC output make a transition to another voltage level and
absolute current increases from zero through a wire of inductance L.Factors such as process, ambient temperature, voltage, location of output pads, and number of simultaneous
switching output pads determine the magnitude of inductive switching noise.
To control inductive switching noise, enough power and ground pads mustbe assigned and placed correctly. This way the noise magnitude will be limited. This noise reduction will prevent inputs of ASIC design from interpreting the noise as valid logic level.
Successful reduction of inductive switching noise can be accomplished by
the following:
- Reduce the number of outputs that switch simultaneously by dividinthem into groups with each group having a number of delay buffers inserted into their data paths
- Reduce the effective power and ground pin inductance by assigning as many power and ground pads as possible
Sunday, April 18, 2010
Macro Placement
Macro placement takes place after I/O placement.Macro placement can be done manually or automated.
The physical measure of the quality of placement of macros can be as follows:
1.wire length
2.data flow
3.port accessibility
4.timing
Placement of the macro should not lead to segmented floor plan.In a segmented floor plan , standard cells area is not continuous.There is excessive interconnections between the standard cells located at the bottom of the die to those located at the top.This leads to increase in wire length.
To avoid segmentation , macro should be placed such that standard cell area is continuous.Macros could be kept along the ASIC core area.
Segmented Floor Plan
There can be increase in wire length due to the orientation of macro placement and pin locations, to nets being connected may be of different length.Macros should be placed accordingly so that their ports are facing the core area or to the standard cells, orientation should match available routing layers.
Floor plan with Macros Facing Standard Cells Region.
Placement of macro relative to standard cell placement and macro port accessibility has an impact on chip's final routing.The global router gives a statistical and graphical report on the analysis of routing congestion.
Routing congestion is caused by not enough space to provide routing channels between the macros for I/O connection and macro;routing is prohibited and standard cells trap pockets at the edges of the macros or within the corners of the floor plan.
Standard cell trap pockets are long, thin channels between macros.If there are more cells in the channel then it may cause routing congestion.Therefore,these channels need to be kept free for most standard cells and should be available for repeater or buffer insertion
Floor plan with Standard Cells Trap Pocket
Blockage layers:
Most Physical designs require keep-out regions or buffer only which is defined by blockage layer ,which refrain placer from moving the standard cells into this region.
Blockage layers avoid routing congestion.Suppose a macro blocks routing layers and then wire try to detour along the corners of the macros causing congestion at the corners.Blockage layer can be placed at the corners of the macros to reserve resources for the router.These are placed over pre-placed macros covering the power and ground rings.
Naturally, the wires that are used in keep-out regions have a tendency to be long. By allowing buffer insertion in those areas by using a buffer-only region (or blockage), the placer will taper these long nets and thus avoid the long transition times associated with them.
Fly lines:
After macro placement and standard cells are placed , connectivity analysis is performed.This is done by the fly lines.This is to study the connections between i/o pads,macros, standard cells.One can identify seeing the fly lines that whether moving or rotating the macros can reduce wire length which improve routability during floor planning stage.
The physical measure of the quality of placement of macros can be as follows:
1.wire length
2.data flow
3.port accessibility
4.timing
Placement of the macro should not lead to segmented floor plan.In a segmented floor plan , standard cells area is not continuous.There is excessive interconnections between the standard cells located at the bottom of the die to those located at the top.This leads to increase in wire length.
To avoid segmentation , macro should be placed such that standard cell area is continuous.Macros could be kept along the ASIC core area.
Segmented Floor Plan
There can be increase in wire length due to the orientation of macro placement and pin locations, to nets being connected may be of different length.Macros should be placed accordingly so that their ports are facing the core area or to the standard cells, orientation should match available routing layers.
Floor plan with Macros Facing Standard Cells Region.
Placement of macro relative to standard cell placement and macro port accessibility has an impact on chip's final routing.The global router gives a statistical and graphical report on the analysis of routing congestion.
Routing congestion is caused by not enough space to provide routing channels between the macros for I/O connection and macro;routing is prohibited and standard cells trap pockets at the edges of the macros or within the corners of the floor plan.
Standard cell trap pockets are long, thin channels between macros.If there are more cells in the channel then it may cause routing congestion.Therefore,these channels need to be kept free for most standard cells and should be available for repeater or buffer insertion
Floor plan with Standard Cells Trap Pocket
Blockage layers:
Most Physical designs require keep-out regions or buffer only which is defined by blockage layer ,which refrain placer from moving the standard cells into this region.
Blockage layers avoid routing congestion.Suppose a macro blocks routing layers and then wire try to detour along the corners of the macros causing congestion at the corners.Blockage layer can be placed at the corners of the macros to reserve resources for the router.These are placed over pre-placed macros covering the power and ground rings.
Naturally, the wires that are used in keep-out regions have a tendency to be long. By allowing buffer insertion in those areas by using a buffer-only region (or blockage), the placer will taper these long nets and thus avoid the long transition times associated with them.
Fly lines:
After macro placement and standard cells are placed , connectivity analysis is performed.This is done by the fly lines.This is to study the connections between i/o pads,macros, standard cells.One can identify seeing the fly lines that whether moving or rotating the macros can reduce wire length which improve routability during floor planning stage.
Saturday, April 17, 2010
Low power design techniques
Why Low power in today's chip design ?
Dynamic power reduction techniques:
Power optimization techniques can be introduced at the RTL level.
This includes:
We have many flip flops in our design.So there is clock transitioning continuously happening at the clock inputs of these flip flops.This contributes to dynamic power dissipation due to switching activity of the clock.
If the clock is gated and then sent to the flip flops , seems to reduce power dissipation than the one which is not gated.
The amount of power saving increases with increase in the number of registers.
FSM encoding:
Power reduction can be done at the algorithmic level by using proper encoding scheme for FSM state assignments.This depends on the transitions that take place while going from one state to next state.
Say from 3 to 4 in binary encoding scheme requires 3 transitions, while gray -code representation requires only one.
Less power is consumed when FSM state use gray-code encoding scheme.
Bus encoding:
Gray coding is also useful for power reduction n SOC bus interconnects.
Dynamic power in this case depends on the width of the bus and loading capacitance, so bus segmentation will naturally help in power reduction by reducing capacitance in bus segment.
In Bus, BI bus invert coding is implemented , where in it is decided whether to send actual data or its complement depending on the transitions on bus interconnect.This depends on the hamming distance between the present and the next state.If the hamming distance is greater than the half of width of the bus ,then next bus value is the complement of the next data of the bus.If the hamming distance is less than the half of the width of the bus , then the data sent is actual data.
Deglitching:
Power dissipation occurs due to the switching activity in cmos logic gates.Power can be saved significantly if the unnecessary switching can be avoided.Glitches are the unwanted momentary transitions that occur due to the delay in logic gates.
Glitches add to the number of transitions , they should be avoided.
The arithmetic operations are prone to produce glitches, if all the multiplies and adders are sequential and latches are not provided to hold their values until they become stable.Latches
hold the previous input value at each level thus avoiding glitches .
Another low power design technique is to replace flip flops with latches wherever possible.
Both latches and flip flops are building blocks of sequentialcircuits and their outputs depend on the current inputs as well as previous inputs and outputs.
The difference between latches and flip flop is that latches are level sensitive and flip flops are edge sensitive.
In D-latch, output Q obtain the value of the D-input at the specified level of the clock signal,it responds to the changes in the input as long as clock signal is asserted.
In D-flip-flop,output responds to changes in the input at the specified edges of the clock signal, thus preventing the output to respond to changes in the input after the rising or falling edge .The output of the flip flop remains constant even if the input changes after the rising or falling edge.
Multi-Threshold -
This techniques uses both low Vt and high Vt cells.Low -vt cells can be used in critical path while high -Vt cells off the critical path.This improves performance without increase in power.
The flip side of this technique that :
multi -vt cells causes fabrication complexity and increases design time.Improper optimization of the design may utilize more Low Vt cells and hence could end up with increased power.
Multi-Vdd (Voltage)
Power supply is directly proportional to dynamic power.Reducing voltage reduces dynamic power .But lower threshold voltage causes delay in the logic gates.Higher voltage can be applied to timing critical path and rest of the chip runs in lower voltage.Different blocks have different voltages which can be integrated in SOC. This increases power planning complexity in terms of laying down the power rails and power grid structure. Level shifters are necessary to interface between different blocks.
Power Gating:
Power gating is where the circuit blocks not in operation are temporarily turned off going to low power mode.And when they are required in operation, turned on to active mode.The goal of power gating is to reduce leakage power by temporarily turning off the circuit blocks and switching the two modes in a suitable manner so to reduce its impact on performance and maximize power performance.
It increases time delay as the gated modes should be safely entered and exited.
Dynamic power reduction techniques:
Power optimization techniques can be introduced at the RTL level.
This includes:
- Clock gating
- FSM encoding
- Avoiding glitches or Deglitching
- bus encoding
We have many flip flops in our design.So there is clock transitioning continuously happening at the clock inputs of these flip flops.This contributes to dynamic power dissipation due to switching activity of the clock.
If the clock is gated and then sent to the flip flops , seems to reduce power dissipation than the one which is not gated.
The amount of power saving increases with increase in the number of registers.
FSM encoding:
Power reduction can be done at the algorithmic level by using proper encoding scheme for FSM state assignments.This depends on the transitions that take place while going from one state to next state.
Say from 3 to 4 in binary encoding scheme requires 3 transitions, while gray -code representation requires only one.
Less power is consumed when FSM state use gray-code encoding scheme.
Bus encoding:
Gray coding is also useful for power reduction n SOC bus interconnects.
Dynamic power in this case depends on the width of the bus and loading capacitance, so bus segmentation will naturally help in power reduction by reducing capacitance in bus segment.
In Bus, BI bus invert coding is implemented , where in it is decided whether to send actual data or its complement depending on the transitions on bus interconnect.This depends on the hamming distance between the present and the next state.If the hamming distance is greater than the half of width of the bus ,then next bus value is the complement of the next data of the bus.If the hamming distance is less than the half of the width of the bus , then the data sent is actual data.
Deglitching:
Power dissipation occurs due to the switching activity in cmos logic gates.Power can be saved significantly if the unnecessary switching can be avoided.Glitches are the unwanted momentary transitions that occur due to the delay in logic gates.
Glitches add to the number of transitions , they should be avoided.
The arithmetic operations are prone to produce glitches, if all the multiplies and adders are sequential and latches are not provided to hold their values until they become stable.Latches
hold the previous input value at each level thus avoiding glitches .
Another low power design technique is to replace flip flops with latches wherever possible.
Both latches and flip flops are building blocks of sequentialcircuits and their outputs depend on the current inputs as well as previous inputs and outputs.
The difference between latches and flip flop is that latches are level sensitive and flip flops are edge sensitive.
In D-latch, output Q obtain the value of the D-input at the specified level of the clock signal,it responds to the changes in the input as long as clock signal is asserted.
In D-flip-flop,output responds to changes in the input at the specified edges of the clock signal, thus preventing the output to respond to changes in the input after the rising or falling edge .The output of the flip flop remains constant even if the input changes after the rising or falling edge.
Multi-Threshold -
This techniques uses both low Vt and high Vt cells.Low -vt cells can be used in critical path while high -Vt cells off the critical path.This improves performance without increase in power.
The flip side of this technique that :
multi -vt cells causes fabrication complexity and increases design time.Improper optimization of the design may utilize more Low Vt cells and hence could end up with increased power.
Multi-Vdd (Voltage)
Power supply is directly proportional to dynamic power.Reducing voltage reduces dynamic power .But lower threshold voltage causes delay in the logic gates.Higher voltage can be applied to timing critical path and rest of the chip runs in lower voltage.Different blocks have different voltages which can be integrated in SOC. This increases power planning complexity in terms of laying down the power rails and power grid structure. Level shifters are necessary to interface between different blocks.
Power Gating:
Power gating is where the circuit blocks not in operation are temporarily turned off going to low power mode.And when they are required in operation, turned on to active mode.The goal of power gating is to reduce leakage power by temporarily turning off the circuit blocks and switching the two modes in a suitable manner so to reduce its impact on performance and maximize power performance.
It increases time delay as the gated modes should be safely entered and exited.
Monday, April 12, 2010
Power dissipation in CMOS
Power dissipation in CMOS comes from two components:
Static dissipation due to:
1.sub threshold conduction while the transistor is OFF.
2.Tunneling current through gate oxide.
3Leakage current through reverse biased diodes.
Dynamic dissipation due to:
1.charging and discharging of input and load capacitance.
2.short circuit current while both PMOS and NMOS networks are ON.
Ptotal = Pstatic + Pdynamic
Let us see one by one:
Static power dissipation
Subthreshold Leakage:
The V-I characteristics of transistor shows that current Id flows only when gate to source voltage Vgs > Vt.But in reality when Vgs < Vt ,the transistor does not become OFF, there is some leakage,given by following expression.
Leakage = exp(-qVt/kT)
This happens due to carrier diffusion from source to drain in weak inversion.
So static power dissipation depend on temperature .So ,when chip heats up static power dissipation also exponentially increases.
Gate oxide tunneling:
When a high electric field is applied to gate oxide ,electrons may tunnel into gate oxide layer if it is less than 3-4nm thick which results in leakage.This leakage current exponentially depends on oxide thickness and Vdd.Electrons may tunnel into conduction band of the oxide layer.
There is finite probability that carriers may tunnel into gate oxide causing gate leakage current flowing into the gate.
Junction Leakage:
There are many parasitic diodes which are formed for e.g, p-n junction between diffusion and substrate or well form diodes.To make these diodes reverse biased ,substrate is connected to GND and n-well to VDD .But these reverse biased diodes conduct a small amount of current.
Ireverse=A.Js.(e(q.Vbias/kT)-1)
Vbias-->reverse bias voltage across the junction
Js-->reverse satuartion current density
A-->junction area
Junction leakage is caused by diffusion and drift of minority carriers at the edges of depletion region and generation of electron -hole pair in the depletion region of the reverse biased junctions.
Dynamic Power Dissipation
Dynamic power dissipation occur when signal flow through CMOS logic circuit which change logic state.Power is drawn from power supply to charge the output node capacitance.
The output node capacitance consists of the following:
1.Output node capacitance of the logic gate:This is due to drain diffusion region.
2.Total interconnect capacitance.
3.Input node capacitance of the driven gate :This is due to the gate oxide capacitance.
Let us consider this inverter circuit .Power is consumed from the power supply to charge the output node capacitance. Power drawn from power supply is dissipated in PMOS during charge up and charge down process dissipates power in NMOS transistor.
Only half of the power is stored as energy in capacitance,
Therefore energy stored in capacitor is= CL.VDD2 / 2.The other half is dissipated as heat in PMOS transistor.We see that energy dissipation in PMOS is independent of the size of PMOS.
This energy is then dissipated as heat in NMOS transistor.During discharge phase charge is removed from the capacitor and its energy is dissipated as heat in NMOS.
Each switching cycle takes a fixed amount of energy = CL. VDD2.
If a gate is switched on and off ‘fn’ times / second, then Pdynamic = CL. VDD2. fn.
Below mentioned steps can be taken to reduce dynamic power
1) Reduce power supply voltage Vdd
2) Reduce voltage swing in all nodes
3) Reduce the switching probability (transition factor)
4) Reduce load capacitance
Short Circuit Power:
The finite rise and fall time of the input to the CMOS logic gates causes a direct current path from VDD to Gnd,this exist for short duration during switching.
During switching both NMOS and PMOS are simultaneously turned ON,especially when the condition ,VTn < Vin < Vdd - |VTp| holds for the input voltage, where VTn and VTp are NMOS and PMOS thresholds, there will be a conductive path open between Vdd and GND because both the NMOS and PMOS devices will be simultaneously on.
When the input voltage exceeds threshold voltage VTn the NMOS starts conducting and until input voltage reaches Vdd-|Vtp| PMOS is ON.Thus for some time bot transistor are ON.Similar event causes short circuit current to flow when signal is falling.Short circuit current terminates when transition is completed.
short circuit current is directly dependent on rise time and fall time, reducing transition short circuit component decreases.But propagation delay need to be considered.
when input rise and fall time is greater than the output rise and fall time ,short circuit path will be for longer time ,so it is desirable to have equal rise and fall time edges.
also, if Vdd is less than the sum of Vtn and Vtp then short circuit current can be eliminated since there is no way that both transistor can be turned on for any input voltage.
Static dissipation due to:
1.sub threshold conduction while the transistor is OFF.
2.Tunneling current through gate oxide.
3Leakage current through reverse biased diodes.
Dynamic dissipation due to:
1.charging and discharging of input and load capacitance.
2.short circuit current while both PMOS and NMOS networks are ON.
Ptotal = Pstatic + Pdynamic
Let us see one by one:
Static power dissipation
Subthreshold Leakage:
The V-I characteristics of transistor shows that current Id flows only when gate to source voltage Vgs > Vt.But in reality when Vgs < Vt ,the transistor does not become OFF, there is some leakage,given by following expression.
Leakage = exp(-qVt/kT)
This happens due to carrier diffusion from source to drain in weak inversion.
So static power dissipation depend on temperature .So ,when chip heats up static power dissipation also exponentially increases.
Gate oxide tunneling:
When a high electric field is applied to gate oxide ,electrons may tunnel into gate oxide layer if it is less than 3-4nm thick which results in leakage.This leakage current exponentially depends on oxide thickness and Vdd.Electrons may tunnel into conduction band of the oxide layer.
There is finite probability that carriers may tunnel into gate oxide causing gate leakage current flowing into the gate.Junction Leakage:
There are many parasitic diodes which are formed for e.g, p-n junction between diffusion and substrate or well form diodes.To make these diodes reverse biased ,substrate is connected to GND and n-well to VDD .But these reverse biased diodes conduct a small amount of current.
Ireverse=A.Js.(e(q.Vbias/kT)-1)
Vbias-->reverse bias voltage across the junction
Js-->reverse satuartion current density
A-->junction area
Junction leakage is caused by diffusion and drift of minority carriers at the edges of depletion region and generation of electron -hole pair in the depletion region of the reverse biased junctions.
Dynamic Power Dissipation
Dynamic power dissipation occur when signal flow through CMOS logic circuit which change logic state.Power is drawn from power supply to charge the output node capacitance.
The output node capacitance consists of the following:
1.Output node capacitance of the logic gate:This is due to drain diffusion region.
2.Total interconnect capacitance.
3.Input node capacitance of the driven gate :This is due to the gate oxide capacitance.
Let us consider this inverter circuit .Power is consumed from the power supply to charge the output node capacitance. Power drawn from power supply is dissipated in PMOS during charge up and charge down process dissipates power in NMOS transistor.Only half of the power is stored as energy in capacitance,
Therefore energy stored in capacitor is= CL.VDD2 / 2.The other half is dissipated as heat in PMOS transistor.We see that energy dissipation in PMOS is independent of the size of PMOS.
This energy is then dissipated as heat in NMOS transistor.During discharge phase charge is removed from the capacitor and its energy is dissipated as heat in NMOS.
Each switching cycle takes a fixed amount of energy = CL. VDD2.
If a gate is switched on and off ‘fn’ times / second, then Pdynamic = CL. VDD2. fn.
Below mentioned steps can be taken to reduce dynamic power
1) Reduce power supply voltage Vdd
2) Reduce voltage swing in all nodes
3) Reduce the switching probability (transition factor)
4) Reduce load capacitance
Short Circuit Power:
The finite rise and fall time of the input to the CMOS logic gates causes a direct current path from VDD to Gnd,this exist for short duration during switching.
During switching both NMOS and PMOS are simultaneously turned ON,especially when the condition ,VTn < Vin < Vdd - |VTp| holds for the input voltage, where VTn and VTp are NMOS and PMOS thresholds, there will be a conductive path open between Vdd and GND because both the NMOS and PMOS devices will be simultaneously on.
When the input voltage exceeds threshold voltage VTn the NMOS starts conducting and until input voltage reaches Vdd-|Vtp| PMOS is ON.Thus for some time bot transistor are ON.Similar event causes short circuit current to flow when signal is falling.Short circuit current terminates when transition is completed.
short circuit current is directly dependent on rise time and fall time, reducing transition short circuit component decreases.But propagation delay need to be considered.
when input rise and fall time is greater than the output rise and fall time ,short circuit path will be for longer time ,so it is desirable to have equal rise and fall time edges.
also, if Vdd is less than the sum of Vtn and Vtp then short circuit current can be eliminated since there is no way that both transistor can be turned on for any input voltage.
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