Chip level Floorplanning

1.Floor plan should be started with I/Os at the periphery (depending on package design).
2.The blocks in the chip which require special design needs should be accommodated.
For ex -PLL,analog block,blocks that require different voltage , block that work with double speed clock.Suppose a flash memory has high programming voltage input then it should be placed closer to the i/o pins.
3.If there are more than two or three larger blocks or other features which would make the present floor plan an impossible one , then business decisions can be taken whether to increase the die size ,which is financially viable with larger and expensive die?Or can it be solved by rearranging the i/os.If any of the larger blocks are soft IP or available as RTL code so that it might avoid going for a larger die by repartitioning the blocks into smaller ones.
4.RTL should be examined for logical models to break out into hierarchical physical elements.If there are multiple instances of hierarchical logical element then they should be grouped into one physical element.
5.It is easy to floor plan the same size blocks so small blocks should be grouped together.
6.Floor Planning can be completed by placing rest of the blocks in the remaining space available based on their i/o and power consumption.
7.It is better to avoid placing blocks that consume more power at the center of the chip.