I am interested in becoming custom Layout engineer as well as ASIC backend.I understand my role includes:
ASIC backend --Floor planning, Placement,Clock tree synthesis,routing,Physical verification -Design rule check,Layout vs schematic and Parasitic extraction,Back annotation Static timing analysis,tape out GDS-ll .
Layout -Layout construction,Design rule check,Layout vs schematic,Parasitic extraction,
Schematic Back annotation, Re simulation,chip or module ok.
Physical design comes after the front end which includes from system specification to functional design where we generate gate level netlist mapped to standard cell library.Physical design and beyond forms the back end flow.
Layout is done once circuit is simulated ,its functionality is verified and whether the functionality is what is intended ,and should meet the specifications.
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