Latch Up

Latch-up is a condition in which parasitic components give rise to the low-resistance conducting path between the power rails i.e. vdd to Vss causing disastrous results.

Caused due to the glitches on power rails

How it works ?


















Here image shows the key parasitic components associated with a p-well structure.

In effect, 2 transistors and 2 resistance forms a path between Vdd and Vss. If sufficient subrate current flows to generate enough volatge across substarte resistance Rs to turn on transistor T1, this will then draw current through pwell resistance Rp and if the voltage developed is sufficient then transistor T2 turns on establishing low-resistance oath between the supply rails. If current gain of the 2 transistor are such that b1xb2>1 then latch may occur.


How to avoid latch up ?

Introduction of gaurd rings

Increase in sub doping which inturn decreases value of Rs

Rp can be reduced by control of fabrication parameters ensuring low contact resistance to Vss

http://cnx.org/content/m1031/latest/

Floor Plan

Voltage transfer characteristics

The voltage transfer characteristics can be obtained by superimposing current characteristics of NMOS and PMOS devices.This is called a load-line plot.

Idsp = -Idsn
Vgsn =Vin; Vgsp = Vin -Vdd
Vdsn = Vout ; Vdsp = Vout - Vdd

• The VTC of the inverter hence exhibits a very narrow transition zone. This results fromthe high gain during the switching transient, when both NMOS and PMOS are simultaneously on, and in saturation. In that operation region, a small change in the input voltage results in a large output variation

CMOS inverter

The static cmos inverter:
When Vin is high and equal to Vdd,the NMOS transistor is on,while PMOS transistor is off.A direct path exist between Vout and ground node,resulting steady-state value of 0v.On the other hand , when Vin is low (0v),NMOS and PMOS transistors are off and on respectively.A direct path exist between Vdd and Vout yielding a high output voltage.

Other important properties:

• The high and low output levels equal VDD and GND, respectively; in other words,the voltage swing is equal to the supply voltage. This results in high noise margins.
• The logic levels are not dependent upon the relative device sizes, so that the transistors can be minimum size. Gates with this property are called ratioless.
• In steady state , there always exists a path with finite resistance between the output and either Vdd or Gnd.A well-designed CMOS inverter ,therefore has a low output impedances, which makes it less sensitive to noise and disturbances.
• The input resistance of the CMOS inverter is extremely high , as the gate of MOS transistor is a virtually perfect insulator and draws no dc input current.Since the input node of the inverter only connect to transistor gates,the steady state input current is nearly zero.
• A single inverter can theoretically have infinite fanout and still be functionally operational.However, increasing fan-out also increases propagation delay.
• No direct path exist between VDD and gnd under steady state operating condition,absence of current indicates that the gate does not consume any static power.

Clock tree synthesis

why CTS?
Logical proximity does not mean physical proximity of related flops.Interconnect delays will degrade the quality of clock signal.Clock are treated as ideal during synthesis.
To meet the specified clock skew and insertion delay.

CTS specification:

Clock tree synthesis has the following clock tree synthesis specifications:

• Target transition delay
  
• Target load capacitance
  
• Target fanout
  

Clock tree
Path from the clock source to clock sink pins of the flops or macro cells.
Clock tree begins from SDC specified clock source and ends at astro-defined stop pins.

Stop pins are
Sync pins: clock pins of the sequential circuit and macro cells.
Sequential cells’ clock port with trigger edge information contained in library.
Ignore pins: Ignore pins are the stop points of the clock tree.Clock tree synthesis does not balance delays for ignore pins.
For eg
Sequential gate’s non-clock port, such as set/reset,Logic gate’s output pin without a connection to a net.


Clock tree is constructed by inverter and buffers available in the library.

Clock tree synthesis has the following clock tree constraints:

• Maximum transition delay-It limits the maximum transition delay time each clock net may have.
  
• Maximum load capacitance-It limits the load capacitance (wire and pin) each buffer in the clock tree may drive.
  
• Maximum fanout-It limits the fanout each buffer in the clock tree may drive.
  
• Maximum buffer level-It is important to understand that this constraint will be applied per gate level; that is, if your clock tree has several serial gating cells, each sub tree can have up to "rule maximum buffer levels" levels.Another thing to note is that when the maximum of levels is reached, clock tree synthesis will stop any further processing

Optimization in CTS:

• Buffer sizing and gate sizing-all gating cells in the clock tree will be sized to their largest available drive strength before any other processing is done.
• Delay insertion
• Buffer gate relocation-With this parameter, all gating cells in the clock tree will be moved to be located at the center of their fanout
• Dummy load
• level adjustment

Effect of CTS:
clock buffers are added.
Congestion may increase.
Non clock tree cells may be moved to less ideal locations.
Can introduce new timing and max trans/cap violations.

Reconnect the scan chains:
Scan chains are disconnected prior to placement to allow placement to focus on functional paths.
Reconnect scan chains so that they are included for hold time fixing.Different ordering based on placement to minimize routing resources.

After CTS actual clock network delay can be calculated instead of ideal values from SDC.

Clock tree optimization:
Perform additional clock tree optimization as necessary to further improve clock skew and insertion delay before routing.


what will you do if setup is till violating when clock tree is perfectly balanced?
Useful skew optimization is performed.It fixes setup timing violation using positive slack in the pipeline through clock push/pull.

Post route optimization should not be performed when useful skew CTO was executed.Post route CTO focuses on balancing skew which will undo the useful skew optimization.

If clock is skewed intentionally to improve setup slack then it is known as useful skew.

Routing Flow

Route Clock nets

↓

Route signal nets

↓

optimize trace topology

↓

Post route clock tree optimization

↓

all nets routed

↓

skew and timing ok? no→ Post route CTO
↓yes
Search and repair

Route clock nets:
To meet the specified insertion delay and skew it is necessary that clock nets be routed first, they can have the most direct-routing.
This also indicates to route the critical signals and buses in the design.


Route signal nets:
After the critical nets are routed the signal nets non-critical ca be routed.The process of routing is timing-driven.Routing of timing critical path is given highest priority in order to maintain the overall timing so that the route is as short as possible.Nets that are non-critical are routed around critical areas to provide more wiring area for critical nets.



Post route CTO:
Minor clock skew and timing violations may have been introduced by previous routing and optimization steps,which are fixed in this step.